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Searched +full:kpss +full:- +full:acc (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/power/
H A Dqcom,kpss-acc-v2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
10 - Christian Marangi <ansuelsmth@gmail.com>
13 The KPSS ACC provides clock, power manager, and reset control to a Krait CPU.
14 There is one ACC register region per CPU within the KPSS remapped region as
15 well as an alias register region that remaps accesses to the ACC associated
16 with the CPU accessing the region. ACC v2 is currently used as a
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,kpss-acc-v1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
10 - Christian Marangi <ansuelsmth@gmail.com>
13 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
14 There is one ACC register region per CPU within the KPSS remapped region as
15 well as an alias register region that remaps accesses to the ACC associated
16 with the CPU accessing the region. ACC v1 is currently used as a
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
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H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
11 #include <dt-bindings/gpio/gpio.h>
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H A Dqcom-msm8226.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
12 #include <dt-bindings/clock/qcom,rpmcc.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,saw2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 power-controller that transitions a piece of hardware (like a processor or
27 - enum:
28 - qcom,ipq4019-saw2-cpu
29 - qcom,ipq4019-saw2-l2
30 - qcom,ipq8064-saw2-cpu
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/linux/arch/arm/mach-qcom/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
59 node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); in scss_release_secondary()
62 return -ENXIO; in scss_release_secondary()
68 return -ENOMEM; in scss_release_secondary()
88 return -ENODEV; in cortex_a7_release_secondary()
90 acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); in cortex_a7_release_secondary()
92 ret = -ENODEV; in cortex_a7_release_secondary()
98 ret = -ENOMEM; in cortex_a7_release_secondary()
144 return -ENODEV; in kpssv1_release_secondary()
146 acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); in kpssv1_release_secondary()
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/linux/drivers/clk/qcom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
1411 Say Y if you want to toggle LPASS-adjacent resets within
1529 tristate "High-Frequency PLL (HFPLL) Clock Controller"
1531 Support for the high-frequency PLLs present on Qualcomm devices.
1536 tristate "KPSS Clock Controller"
1538 Support for the Krait ACC and GCC clock controllers. Say Y