Home
last modified time | relevance | path

Searched +full:keystone +full:- +full:irq (Results 1 – 25 of 26) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dti,keystone-irq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ti,keystone-irq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 IRQ controller IP
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ
14 controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on
17 Keystone SOCs.
21 const: ti,keystone-irq
[all …]
H A Dti,keystone-irq.txt1 Keystone 2 IRQ controller IP
3 On Keystone SOCs, DSP cores can send interrupts to ARM
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
5 The IRQ handler running on HOST OS can identify DSP signal source by
7 used by the IPC mechanism used on Keystone SOCs.
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
[all …]
H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
26 +-------+ | +------+ +-----+ | controller
[all …]
H A Dti,sci-intr.txt10 +----------------------+
12 +-------+ | +------+ +-----+ |
13 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
14 +-------+ | +------+ +-----+ | controller
15 | . . | +-------+
16 +-------+ | . . |----->| IRQ |
17 | INTA |----------->| . . | +-------+
18 +-------+ | . +-----+ |
19 | +------+ | N | |
20 | | irqM | +-----+ |
[all …]
H A Dti,sci-inta.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
22 +-----------------------------------------+
24 | +--------------+ +------------+ |
25 m ------>| | vint | bit | | 0 |.....|63| vint0 |
26 . | +--------------+ +------------+ | +------+
[all …]
H A Dti,sci-inta.txt11 +-----------------------------------------+
13 | +--------------+ +------------+ |
14 m ------>| | vint | bit | | 0 |.....|63| vint0 |
15 . | +--------------+ +------------+ | +------+
17 Globalevents ------>| . . |------>| IRQ |
19 . | . . | +------+
20 n ------>| +--------------+ +------------+ |
22 | +--------------+ +------------+ |
24 +-----------------------------------------+
36 Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dti,keystone-dsp-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 DSP GPIO controller
10 - Grygorii Strashko <grygorii.strashko@ti.com>
14 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
15 This is one of the component used by the IPC mechanism used on Keystone SOCs.
18 - 8 for C66x CorePacx CPUs 0-7
20 Keystone 2 DSP GPIO controller has specific features:
[all …]
H A Dgpio-dsp-keystone.txt1 Keystone 2 DSP GPIO controller bindings
4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
5 This is one of the component used by the IPC mechanism used on Keystone SOCs.
8 - 8 for C66x CorePacx CPUs 0-7
10 Keystone 2 DSP GPIO controller has specific features:
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
17 - compatible: should be "ti,keystone-dsp-gpio"
18 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
[all …]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dti,keystone-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ti,keystone-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI Keystone timer
10 - Alexander A. Klimov <grandmaster@al2klimov.de>
11 - Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
14 A 64-bit timer in the KeyStone architecture devices. The timer can be
15 configured as a general-purpose 64-bit timer, dual general-purpose 32-bit
16 timers. When configured as dual 32-bit timers, each half can operate in
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-keystone.txt1 TI Keystone PCIe interface
3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
21 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
[all …]
H A Dti,am65-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - ti,am654-pcie-rc
20 - ti,keystone-pcie
25 reg-names:
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/gpio/gpio.h>
10 compatible = "ti,keystone";
11 model = "Texas Instruments Keystone 2 SoC";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
30 gic: interrupt-controller@2561000 {
[all …]
H A Dkeystone-k2g.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/keystone.h>
10 #include <dt-bindings/gpio/gpio.h>
13 compatible = "ti,k2g","ti,keystone";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
32 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dbosch,c_can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Dario Binacchi <dariobin@libero.it>
15 - $ref: can-controller.yaml#
20 - enum:
21 - bosch,c_can
22 - bosch,d_can
23 - ti,dra7-d_can
24 - ti,am3352-d_can
[all …]
H A Dc_can.txt2 -------------------------------------------------
5 - compatible : Should be "bosch,c_can" for C_CAN controllers and
7 Can be "ti,dra7-d_can", "ti,am3352-d_can" or
8 "ti,am4372-d_can".
9 - reg : physical base address and size of the C_CAN/D_CAN
11 - interrupts : property with a value describing the interrupt
15 - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the
18 The following are mandatory properties for Keystone 2 66AK2G SoCs only:
19 - power-domains : Should contain a phandle to a PM domain provider node
22 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,k2g-dss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
15 The K2G DSS is an ultra-light version of TI Keystone Display
21 const: ti,k2g-dss
25 - description: cfg DSS top level
26 - description: common DISPC common
[all …]
H A Dti,j721e-dss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
15 The J721E TI Keystone Display SubSystem with four output ports and
22 const: ti,j721e-dss
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
[all …]
H A Dti,am65x-dss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
15 The AM625 and AM65x TI Keystone Display SubSystem has two output
31 - ti,am625-dss
32 - ti,am62a7-dss
33 - ti,am62l-dss
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
24 #address-cells = <2>;
25 #size-cells = <2>;
27 #interrupt-cells = <3>;
[all …]
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
[all …]
H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
[all …]
H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
[all …]
H A Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
[all …]
H A Dk3-j784s4-j742s2-main-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
29 compatible = "mmio-sram";
[all …]
H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]

12