xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt8365-evk.dts (revision ae5de77ed78ae54d86cead5604869212e8008e6b) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <fparent@baylibre.com>
6 * Bernhard Rosenkränzer <bero@baylibre.com>
7 * Alexandre Mergnat <amergnat@baylibre.com>
8 */
9
10/dts-v1/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
15#include "mt8365.dtsi"
16#include "mt6357.dtsi"
17
18/ {
19	model = "MediaTek MT8365 Open Platform EVK";
20	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
21
22	aliases {
23		serial0 = &uart0;
24		ethernet = &ethernet;
25	};
26
27	chosen {
28		stdout-path = "serial0:921600n8";
29	};
30
31	connector {
32		compatible = "hdmi-connector";
33		label = "hdmi";
34		type = "d";
35
36		port {
37			#address-cells = <1>;
38			#size-cells = <0>;
39			hdmi_connector_in: endpoint@0 {
40				reg = <0>;
41				remote-endpoint = <&hdmi_connector_out>;
42			};
43		};
44	};
45
46	firmware {
47		optee {
48			compatible = "linaro,optee-tz";
49			method = "smc";
50		};
51	};
52
53	gpio-keys {
54		compatible = "gpio-keys";
55		pinctrl-names = "default";
56		pinctrl-0 = <&gpio_keys>;
57
58		key-volume-up {
59			gpios = <&pio 24 GPIO_ACTIVE_LOW>;
60			label = "volume_up";
61			linux,code = <KEY_VOLUMEUP>;
62			wakeup-source;
63			debounce-interval = <15>;
64		};
65	};
66
67	memory@40000000 {
68		device_type = "memory";
69		reg = <0 0x40000000 0 0xc0000000>;
70	};
71
72	usb_otg_vbus: regulator-0 {
73		compatible = "regulator-fixed";
74		regulator-name = "otg_vbus";
75		regulator-min-microvolt = <5000000>;
76		regulator-max-microvolt = <5000000>;
77		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
78		enable-active-high;
79	};
80
81	reg_vsys: regulator-vsys {
82		compatible = "regulator-fixed";
83		regulator-name = "vsys";
84		regulator-always-on;
85		regulator-boot-on;
86	};
87
88	touch0_fixed_3v3: regulator-vio33tp {
89		compatible = "regulator-fixed";
90		regulator-name = "vio33_tp";
91		regulator-min-microvolt = <3300000>;
92		regulator-max-microvolt = <3300000>;
93		vin-supply = <&reg_vsys>;
94	};
95
96	reserved-memory {
97		#address-cells = <2>;
98		#size-cells = <2>;
99		ranges;
100
101		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
102		bl31_secmon_reserved: secmon@43000000 {
103			no-map;
104			reg = <0 0x43000000 0 0x30000>;
105		};
106
107		/* 12 MiB reserved for OP-TEE (BL32)
108		 * +-----------------------+ 0x43e0_0000
109		 * |      SHMEM 2MiB       |
110		 * +-----------------------+ 0x43c0_0000
111		 * |        | TA_RAM  8MiB |
112		 * + TZDRAM +--------------+ 0x4340_0000
113		 * |        | TEE_RAM 2MiB |
114		 * +-----------------------+ 0x4320_0000
115		 */
116		optee_reserved: optee@43200000 {
117			no-map;
118			reg = <0 0x43200000 0 0x00c00000>;
119		};
120	};
121
122	sound: sound {
123		compatible = "mediatek,mt8365-mt6357";
124		pinctrl-names = "default",
125				"dmic",
126				"miso_off",
127				"miso_on",
128				"mosi_off",
129				"mosi_on";
130		pinctrl-0 = <&aud_default_pins>;
131		pinctrl-1 = <&aud_dmic_pins>;
132		pinctrl-2 = <&aud_miso_off_pins>;
133		pinctrl-3 = <&aud_miso_on_pins>;
134		pinctrl-4 = <&aud_mosi_off_pins>;
135		pinctrl-5 = <&aud_mosi_on_pins>;
136		mediatek,platform = <&afe>;
137	};
138
139	vsys_lcm_reg: regulator-vsys-lcm {
140		compatible = "regulator-fixed";
141		enable-active-high;
142		gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
143		regulator-max-microvolt = <5000000>;
144		regulator-min-microvolt = <5000000>;
145		regulator-name = "vsys_lcm";
146	};
147
148};
149
150&afe {
151	mediatek,dmic-mode = <1>;
152	status = "okay";
153};
154
155&cpu0 {
156	proc-supply = <&mt6357_vproc_reg>;
157	sram-supply = <&mt6357_vsram_proc_reg>;
158};
159
160&cpu1 {
161	proc-supply = <&mt6357_vproc_reg>;
162	sram-supply = <&mt6357_vsram_proc_reg>;
163};
164
165&cpu2 {
166	proc-supply = <&mt6357_vproc_reg>;
167	sram-supply = <&mt6357_vsram_proc_reg>;
168};
169
170&cpu3 {
171	proc-supply = <&mt6357_vproc_reg>;
172	sram-supply = <&mt6357_vsram_proc_reg>;
173};
174
175&dither0_out {
176	remote-endpoint = <&dsi0_in>;
177};
178
179&dpi0 {
180	pinctrl-0 = <&dpi_default_pins>;
181	pinctrl-1 = <&dpi_idle_pins>;
182	pinctrl-names = "default", "sleep";
183	/*
184	 * Ethernet and HDMI (DPI0) are sharing pins.
185	 * Only one can be enabled at a time and require the physical switch
186	 * SW2101 to be set on LAN position
187	 */
188	status = "disabled";
189
190	ports {
191		#address-cells = <1>;
192		#size-cells = <0>;
193
194		port@0 {
195			#address-cells = <1>;
196			#size-cells = <0>;
197			reg = <0>;
198			dpi0_in: endpoint@1 {
199				reg = <1>;
200				remote-endpoint = <&rdma1_out>;
201			};
202		};
203
204		port@1 {
205			#address-cells = <1>;
206			#size-cells = <0>;
207			reg = <1>;
208			dpi0_out: endpoint@1 {
209				reg = <1>;
210				remote-endpoint = <&it66121_in>;
211			};
212		};
213	};
214};
215
216&dsi0 {
217	#address-cells = <1>;
218	#size-cells = <0>;
219	status = "okay";
220
221	panel@0 {
222		compatible = "startek,kd070fhfid015";
223		reg = <0>;
224		enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>;
225		reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
226		iovcc-supply = <&mt6357_vsim1_reg>;
227		power-supply = <&vsys_lcm_reg>;
228
229		port {
230			#address-cells = <1>;
231			#size-cells = <0>;
232			panel_in: endpoint@0 {
233				reg = <0>;
234				remote-endpoint = <&dsi0_out>;
235			};
236		};
237	};
238	ports {
239		#address-cells = <1>;
240		#size-cells = <0>;
241
242		port@0 {
243			#address-cells = <1>;
244			#size-cells = <0>;
245			reg = <0>;
246			dsi0_in: endpoint@0 {
247				reg = <0>;
248				remote-endpoint = <&dither0_out>;
249			};
250		};
251
252		port@1 {
253			#address-cells = <1>;
254			#size-cells = <0>;
255			reg = <1>;
256			dsi0_out: endpoint@0 {
257				reg = <0>;
258				remote-endpoint = <&panel_in>;
259			};
260		};
261	};
262};
263
264&ethernet {
265	pinctrl-0 = <&ethernet_pins>;
266	pinctrl-names = "default";
267	phy-handle = <&eth_phy>;
268	phy-mode = "rmii";
269	/*
270	 * Ethernet and HDMI (DPI0) are sharing pins.
271	 * Only one can be enabled at a time and require the physical switch
272	 * SW2101 to be set on LAN position
273	 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
274	 */
275	status = "disabled";
276
277	mdio {
278		#address-cells = <1>;
279		#size-cells = <0>;
280
281		eth_phy: ethernet-phy@0 {
282			reg = <0>;
283		};
284	};
285};
286
287&i2c0 {
288	clock-frequency = <100000>;
289	pinctrl-0 = <&i2c0_pins>;
290	pinctrl-names = "default";
291	status = "okay";
292};
293
294&i2c1 {
295	#address-cells = <1>;
296	#size-cells = <0>;
297	clock-div = <2>;
298	clock-frequency = <100000>;
299	pinctrl-0 = <&i2c1_pins>;
300	pinctrl-names = "default";
301	status = "okay";
302
303	it66121_hdmi: hdmi@4c {
304		compatible = "ite,it66121";
305		reg = <0x4c>;
306		#sound-dai-cells = <0>;
307		interrupt-parent = <&pio>;
308		interrupts = <68 IRQ_TYPE_LEVEL_LOW>;
309		pinctrl-0 = <&ite_pins>;
310		pinctrl-names = "default";
311		reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
312		vcn18-supply = <&mt6357_vsim2_reg>;
313		vcn33-supply = <&mt6357_vibr_reg>;
314		vrf12-supply = <&mt6357_vrf12_reg>;
315
316		ports {
317			#address-cells = <1>;
318			#size-cells = <0>;
319
320			port@0 {
321				#address-cells = <1>;
322				#size-cells = <0>;
323				reg = <0>;
324				it66121_in: endpoint@0 {
325					reg = <0>;
326					bus-width = <12>;
327					remote-endpoint = <&dpi0_out>;
328				};
329			};
330
331			port@1 {
332				#address-cells = <1>;
333				#size-cells = <0>;
334				reg = <1>;
335				hdmi_connector_out: endpoint@0 {
336					reg = <0>;
337					remote-endpoint = <&hdmi_connector_in>;
338				};
339			};
340		};
341	};
342
343	touchscreen@5d {
344		compatible = "goodix,gt9271";
345		reg = <0x5d>;
346		interrupts-extended = <&pio 78 IRQ_TYPE_EDGE_FALLING>;
347		pinctrl-names = "default";
348		pinctrl-0 = <&touch_pins>;
349		irq-gpios = <&pio 78 GPIO_ACTIVE_HIGH>;
350		reset-gpios = <&pio 79 GPIO_ACTIVE_LOW>;
351		AVDD28-supply = <&touch0_fixed_3v3>;
352		VDDIO-supply = <&mt6357_vrf12_reg>;
353	};
354};
355
356&mmc0 {
357	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
358	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
359	bus-width = <8>;
360	cap-mmc-highspeed;
361	cap-mmc-hw-reset;
362	hs400-ds-delay = <0x12012>;
363	max-frequency = <200000000>;
364	mmc-hs200-1_8v;
365	mmc-hs400-1_8v;
366	no-sd;
367	no-sdio;
368	non-removable;
369	pinctrl-0 = <&mmc0_default_pins>;
370	pinctrl-1 = <&mmc0_uhs_pins>;
371	pinctrl-names = "default", "state_uhs";
372	vmmc-supply = <&mt6357_vemc_reg>;
373	vqmmc-supply = <&mt6357_vio18_reg>;
374	status = "okay";
375};
376
377&mmc1 {
378	bus-width = <4>;
379	cap-sd-highspeed;
380	cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
381	max-frequency = <200000000>;
382	pinctrl-0 = <&mmc1_default_pins>;
383	pinctrl-1 = <&mmc1_uhs_pins>;
384	pinctrl-names = "default", "state_uhs";
385	sd-uhs-sdr104;
386	sd-uhs-sdr50;
387	vmmc-supply = <&mt6357_vmch_reg>;
388	vqmmc-supply = <&mt6357_vmc_reg>;
389	status = "okay";
390};
391
392&mt6357_pmic {
393	interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
394	interrupt-controller;
395	#interrupt-cells = <2>;
396	mediatek,micbias0-microvolt = <1900000>;
397	mediatek,micbias1-microvolt = <1700000>;
398};
399
400&mt6357_vsim1_reg {
401	regulator-min-microvolt = <1800000>;
402	regulator-max-microvolt = <1800000>;
403};
404
405&pio {
406	aud_default_pins: audiodefault-pins {
407		clk-dat-pins {
408			pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
409				 <MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK>,
410				 <MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK>,
411				 <MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO>;
412		};
413	};
414
415	aud_dmic_pins: audiodmic-pins {
416		clk-dat-pins {
417			pinmux = <MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK>,
418				 <MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0>,
419				 <MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1>;
420		};
421	};
422
423	aud_miso_off_pins: misooff-pins {
424		clk-dat-pins {
425			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53>,
426				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54>,
427				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55>,
428				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56>;
429			input-enable;
430			bias-pull-down;
431			drive-strength = <2>;
432		};
433	};
434
435	aud_miso_on_pins: misoon-pins {
436		clk-dat-pins {
437			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO>,
438				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO>,
439				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0>,
440				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1>;
441			drive-strength = <6>;
442		};
443	};
444
445	aud_mosi_off_pins: mosioff-pins {
446		clk-dat-pins {
447			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49>,
448				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50>,
449				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51>,
450				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52>;
451			input-enable;
452			bias-pull-down;
453			drive-strength = <2>;
454		};
455	};
456
457	aud_mosi_on_pins: mosion-pins {
458		clk-dat-pins {
459			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI>,
460				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI>,
461				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0>,
462				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1>;
463			drive-strength = <6>;
464		};
465	};
466
467	dpi_default_pins: dpi-default-pins {
468		pins {
469			pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
470				 <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
471				 <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
472				 <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
473				 <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
474				 <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
475				 <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
476				 <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
477				 <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
478				 <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
479				 <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
480				 <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
481				 <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
482				 <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
483				 <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
484				 <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
485			drive-strength = <4>;
486		};
487	};
488
489	dpi_idle_pins: dpi-idle-pins {
490		pins {
491			pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
492				 <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
493				 <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
494				 <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
495				 <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
496				 <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
497				 <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
498				 <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
499				 <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
500				 <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
501				 <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
502				 <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
503				 <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
504				 <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
505				 <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
506				 <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
507		};
508	};
509
510	ethernet_pins: ethernet-pins {
511		phy_reset_pins {
512			pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
513		};
514
515		rmii_pins {
516			pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
517				 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
518				 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
519				 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
520				 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
521				 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
522				 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
523				 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
524				 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
525				 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
526				 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
527				 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
528				 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
529				 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
530				 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
531				 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
532		};
533	};
534
535	gpio_keys: gpio-keys-pins {
536		pins {
537			pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
538			bias-pull-up;
539			input-enable;
540		};
541	};
542
543	i2c0_pins: i2c0-pins {
544		pins {
545			pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
546				 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
547			bias-pull-up;
548		};
549	};
550
551	i2c1_pins: i2c1-pins {
552		pins {
553			pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
554				 <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
555			bias-pull-up;
556		};
557	};
558
559	ite_pins: ite-pins {
560		irq_ite_pins {
561			pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
562			input-enable;
563			bias-pull-up;
564		};
565
566		pwr_pins {
567			pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
568				 <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
569			output-high;
570		};
571
572		rst_ite_pins {
573			pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
574			output-high;
575		};
576	};
577
578	mmc0_default_pins: mmc0-default-pins {
579		clk-pins {
580			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
581			bias-pull-down;
582		};
583
584		cmd-dat-pins {
585			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
586				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
587				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
588				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
589				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
590				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
591				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
592				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
593				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
594			input-enable;
595			bias-pull-up;
596		};
597
598		rst-pins {
599			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
600			bias-pull-up;
601		};
602	};
603
604	mmc0_uhs_pins: mmc0-uhs-pins {
605		clk-pins {
606			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
607			drive-strength = <MTK_DRIVE_10mA>;
608			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
609		};
610
611		cmd-dat-pins {
612			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
613				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
614				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
615				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
616				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
617				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
618				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
619				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
620				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
621			input-enable;
622			drive-strength = <MTK_DRIVE_10mA>;
623			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
624		};
625
626		ds-pins {
627			pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
628			drive-strength = <MTK_DRIVE_10mA>;
629			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
630		};
631
632		rst-pins {
633			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
634			drive-strength = <MTK_DRIVE_10mA>;
635			bias-pull-up;
636		};
637	};
638
639	mmc1_default_pins: mmc1-default-pins {
640		cd-pins {
641			pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
642			bias-pull-up;
643		};
644
645		clk-pins {
646			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
647			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
648		};
649
650		cmd-dat-pins {
651			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
652				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
653				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
654				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
655				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
656			input-enable;
657			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
658		};
659	};
660
661	mmc1_uhs_pins: mmc1-uhs-pins {
662		clk-pins {
663			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
664			drive-strength = <8>;
665			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
666		};
667
668		cmd-dat-pins {
669			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
670				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
671				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
672				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
673				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
674			input-enable;
675			drive-strength = <6>;
676			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
677		};
678	};
679
680	touch_pins: touch-pins {
681		ctp-int1-pins {
682			pinmux = <MT8365_PIN_78_CMHSYNC__FUNC_GPIO78>;
683			input-enable;
684			bias-disable;
685		};
686
687		rst-pins {
688			pinmux = <MT8365_PIN_79_CMVSYNC__FUNC_GPIO79>;
689			output-low;
690		};
691	};
692
693	uart0_pins: uart0-pins {
694		pins {
695			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
696				 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
697		};
698	};
699
700	uart1_pins: uart1-pins {
701		pins {
702			pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
703				 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
704		};
705	};
706
707	uart2_pins: uart2-pins {
708		pins {
709			pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
710				 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
711		};
712	};
713
714	usb_pins: usb-pins {
715		id-pins {
716			pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
717			input-enable;
718			bias-pull-up;
719		};
720
721		usb0-vbus-pins {
722			pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
723			output-high;
724		};
725
726		usb1-vbus-pins {
727			pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
728			output-high;
729		};
730	};
731
732	pwm_pins: pwm-pins {
733		pins {
734			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
735				 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
736		};
737	};
738};
739
740&pwm {
741	pinctrl-0 = <&pwm_pins>;
742	pinctrl-names = "default";
743	status = "okay";
744};
745
746&rdma1_out {
747	remote-endpoint = <&dpi0_in>;
748};
749
750&ssusb {
751	dr_mode = "otg";
752	maximum-speed = "high-speed";
753	pinctrl-0 = <&usb_pins>;
754	pinctrl-names = "default";
755	usb-role-switch;
756	vusb33-supply = <&mt6357_vusb33_reg>;
757	status = "okay";
758
759	connector {
760		compatible = "gpio-usb-b-connector", "usb-b-connector";
761		id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
762		type = "micro";
763		vbus-supply = <&usb_otg_vbus>;
764	};
765};
766
767&usb_host {
768	vusb33-supply = <&mt6357_vusb33_reg>;
769	status = "okay";
770};
771
772&uart0 {
773	pinctrl-0 = <&uart0_pins>;
774	pinctrl-names = "default";
775	status = "okay";
776};
777
778&uart1 {
779	pinctrl-0 = <&uart1_pins>;
780	pinctrl-names = "default";
781	status = "okay";
782};
783
784&uart2 {
785	pinctrl-0 = <&uart2_pins>;
786	pinctrl-names = "default";
787	status = "okay";
788};
789