Searched +full:k210 +full:- +full:clint (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Palmer Dabbelt <palmer@dabbelt.com>11 - Anup Patel <anup.patel@wdc.com>14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor16 interrupts. It directly connects to the timer and inter-processor interrupt17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>6 #include <dt-bindings/clock/k210-clk.h>7 #include <dt-bindings/pinctrl/k210-fpioa.h>8 #include <dt-bindings/reset/k210-rst.h>12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits15 #address-cells = <1>;16 #size-cells = <1>;17 compatible = "canaan,kendryte-k210";20 * The K210 has an sv39 MMU following the privileged specification v1.9.[all …]