| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | spacemit,k1-pll.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SpacemiT K1 PLL
10 - Haylen Chu <heylenay@4d2.org>
14 const: spacemit,k1-pll
25 Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL
28 "#clock-cells":
31 See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
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| /linux/drivers/clk/sprd/ |
| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
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| H A D | pll.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Spreadtrum pll clock driver
40 * struct sprd_pll - definition of adjustable pll clock
42 * @reg: registers used to set the configuration of pll clock,
43 * reg[0] shows how many registers this pll clock uses.
44 * @itable: pll ibias table, itable[0] means how many items this
47 * @factors used to calculate the pll clock rate
56 u16 k1; member
73 .k1 = _k1, \
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| /linux/arch/riscv/boot/dts/spacemit/ |
| H A D | k1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/spacemit,k1-syscon.h>
8 /dts-v1/;
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "SpacemiT K1";
13 compatible = "spacemit,k1";
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <24000000>;
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| /linux/sound/soc/intel/boards/ |
| H A D | sof_board_helpers.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <sound/soc-acpi-intel-ssp-common.h>
66 #define SOF_LINK_ORDER(k1, k2, k3, k4, k5, k6, k7) \ argument
67 ((((k1) & SOF_LINK_ORDER_MASK) << (SOF_LINK_ORDER_SHIFT * 0)) | \
78 #define SOF_LINK_IDS(k1, k2, k3, k4, k5, k6, k7) \ argument
79 ((((k1) & SOF_LINK_IDS_MASK) << (SOF_LINK_IDS_SHIFT * 0)) | \
91 * @pll_bypass: true for PLL bypass mode
123 * @ssp_mask_hdmi_in: ssp port mask of HDMI-IN BE link
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| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | ich8lan.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
93 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
106 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
107 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
144 /* Half-duplex collision counts */
162 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
163 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
192 /* Strapping Option Register - RO */
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| H A D | netdev.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 static int debug = -1;
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()
136 writel(val, hw->hw_addr + reg); in __ew32()
140 * e1000_regdump - register printout routine
150 switch (reginfo->ofs) { in e1000_regdump()
164 pr_info("%-15s %08x\n", in e1000_regdump()
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| /linux/drivers/media/usb/gspca/ |
| H A D | stk1135.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
45 /* -- read a register -- */
48 struct usb_device *dev = gspca_dev->dev; in reg_r()
51 if (gspca_dev->usb_err < 0) in reg_r()
58 gspca_dev->usb_buf, 1, in reg_r()
62 index, gspca_dev->usb_buf[0]); in reg_r()
65 gspca_dev->usb_err = ret; in reg_r()
69 return gspca_dev->usb_buf[0]; in reg_r()
72 /* -- write a register -- */
76 struct usb_device *dev = gspca_dev->dev; in reg_w()
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| /linux/sound/pci/ctxfi/ |
| H A D | cthardware.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
28 /* 20k1 models */
202 #define PLL_INT (1 << 10) /* PLL input-clock out-of-range */
209 #define DAI_INT (1 << 3) /* DAI (SR-tracker or SPDIF-receiver) */
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| H A D | cthw20k1.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * This file contains the implementation of hardware access methord for 20k1.
76 * Fixed-point value in 8.24 format for parameter channel */
88 u16 czbfs:1; /* Clear Z-Buffers */
162 return -ENOMEM; in src_get_rsc_ctrl_blk()
180 set_field(&ctl->ctl, SRCCTL_STATE, state); in src_set_state()
181 ctl->dirty.bf.ctl = 1; in src_set_state()
189 set_field(&ctl->ctl, SRCCTL_BM, bm); in src_set_bm()
190 ctl->dirty.bf.ctl = 1; in src_set_bm()
198 set_field(&ctl->ctl, SRCCTL_RSR, rsr); in src_set_rsr()
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| H A D | ctatc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
28 #define MONO_SUM_SCALE 0x19a8 /* 2^(-0.5) in 14-bit floating format */
67 /* 20k1 models */
101 .public_name = "IEC958 Non-audio"},
137 if (!apcm->substream) in ct_map_audio_buffer()
140 runtime = apcm->substream->runtime; in ct_map_audio_buffer()
141 vm = atc->vm; in ct_map_audio_buffer()
143 apcm->vm_block = vm->map(vm, apcm->substream, runtime->dma_bytes); in ct_map_audio_buffer()
145 if (!apcm->vm_block) in ct_map_audio_buffer()
146 return -ENOENT; in ct_map_audio_buffer()
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| /linux/drivers/pinctrl/ |
| H A D | pinctrl-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * based on linux/drivers/pinctrl/pinmux-gemini.c
8 * This is a group-only pin controller.
23 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
30 #define DRIVER_NAME "pinctrl-ep93xx"
49 struct ep93xx_regmap_adev *aux = pmx->aux_dev; in ep93xx_pinctrl_update_bits()
51 aux->update_bits(aux->map, aux->lock, reg, mask, val); in ep93xx_pinctrl_update_bits()
73 * descriptions of the registers, “DeviceCfg” on page 5-25 and “SysCfg” on page 5-34, for a
533 PINCTRL_PIN(143, "AD[4]"), /* K1 */
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