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Searched +full:jh7110 +full:- +full:syscrg (Results 1 – 12 of 12) sorted by relevance

/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
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H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
11 compatible = "pine64,star64", "starfive,jh7110";
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
24 phy-handle = <&phy1>;
25 phy-mode = "rgmii-id";
26 starfive,tx-use-rgmii-clk;
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H A Djh7110-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110.dtsi"
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
25 stdout-path = "serial0:115200n8";
33 gpio-restart {
34 compatible = "gpio-restart";
39 pwmdac_codec: audio-codec {
40 compatible = "linux,spdif-dit";
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dstarfive,jh7110-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/starfive,jh7110-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 TDM Controller
11 integrated in StarFive JH7110 SoC, allowing up to 8 channels of
16 - Walker Chen <walker.chen@starfivetech.com>
19 - $ref: dai-common.yaml#
24 - starfive,jh7110-tdm
31 - description: TDM AHB Clock
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dstarfive,jh7110-aoncrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
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H A Dstarfive,jh7110-syscrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dstarfive,jh7110-mmc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/starfive,jh7110
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dstarfive,jh7110-sys-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 SYS Pin Controller
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
21 - Jianlong Huang <jianlong.huang@starfivetech.com>
25 const: starfive,jh7110-sys-pinctrl
39 interrupt-controller: true
41 '#interrupt-cells':
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dstarfive,jh7110-dphy-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Starfive SoC MIPI D-PHY Tx Controller
10 - Keith Zhao <keith.zhao@starfivetech.com>
11 - Shengyang Chen <shengyang.chen@starfivetech.com>
14 The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer
19 const: starfive,jh7110-dphy-tx
27 clock-names:
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dstarfive,jh7110-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb
18 starfive,stg-syscon:
19 $ref: /schemas/types.yaml#/definitions/phandle-array
21 - items:
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dstarfive,jh7110-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe host controller
10 - Kevin Xie <kevin.xie@starfivetech.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
17 const: starfive,jh7110-pcie
21 - description: NOC bus clock
22 - description: Transport layer clock
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/freebsd/sys/dev/clk/starfive/
H A Djh7110_clk_sys.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 /* Clocks for JH7110 SYS group. PLL driver must be attached before this. */
31 #include <dt-bindings/clock/starfive,jh7110-crg.h>
37 { "starfive,jh7110-syscrg", 1 },
46 /* parents for non-pll SYS clocks */
92 /* non-pll SYS clocks */
165 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in jh7110_clk_sys_probe()
168 device_set_desc(dev, "StarFive JH7110 SYS clock generator"); in jh7110_clk_sys_probe()
181 sc->reset_status_offset = SYSCRG_RESET_STATUS; in jh7110_clk_sys_attach()
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