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Searched +full:jh7110 +full:- +full:crg (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-voutcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-voutcrg
21 - description: Vout Top core
22 - description: Vout Top Ahb
23 - description: Vout Top Axi
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H A Dstarfive,jh7110-ispcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
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H A Dstarfive,jh7110-stgcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-stgcrg
21 - description: Main Oscillator (24 MHz)
22 - description: HIFI4 core
23 - description: STG AXI/AHB
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H A Dstarfive,jh7110-aoncrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
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H A Dstarfive,jh7110-syscrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-syscrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
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H A Dstarfive,jh7110-pll.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PLL Clock Generator
10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
13 SYS-SYSCON node.
18 - Xingyu Wu <xingyu.wu@starfivetech.com>
22 const: starfive,jh7110-pll
28 '#clock-cells':
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/linux/drivers/reset/starfive/
H A Dreset-starfive-jh7110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset driver for the StarFive JH7110 SoC
10 #include <soc/starfive/reset-starfive-jh71x0.h>
12 #include "reset-starfive-jh71x0.h"
14 #include <dt-bindings/reset/starfive,jh7110-crg.h>
55 struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data); in jh7110_reset_probe()
57 void __iomem *base = rdev->base; in jh7110_reset_probe()
60 return -ENODEV; in jh7110_reset_probe()
62 return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node, in jh7110_reset_probe()
63 base + info->assert_offset, in jh7110_reset_probe()
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
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/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 PLL Clock Generator Driver
8 * This driver is about to register JH7110 PLL clock generator and support ops.
9 * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
22 #include <linux/clk-provider.h>
30 #include <dt-bindings/clock/starfive,jh7110-crg.h>
275 return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]); in jh7110_pll_priv_from()
284 regmap_read(regmap, info->offsets.pd, &val); in jh7110_pll_regvals_get()
285 ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd; in jh7110_pll_regvals_get()
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