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/linux/drivers/gpu/drm/amd/amdgpu/
H A Disp_v4_1_1.c1 /* SPDX-License-Identifier: MIT */
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
34 #define ISP_PERFORMANCE_STATE_LOW 0
60 .dev_id = "i2c-ov05c10",
62 GPIO_LOOKUP("amdisp-pinctrl", 0, "enable", GPIO_ACTIVE_HIGH),
69 struct amdgpu_isp *isp = container_of(genpd, struct amdgpu_isp, ispgpd); in isp_poweroff() local
70 struct amdgpu_device *adev = isp->adev; in isp_poweroff()
72 return amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ISP, true, 0); in isp_poweroff()
77 struct amdgpu_isp *isp = container_of(genpd, struct amdgpu_isp, ispgpd); in isp_poweron() local
78 struct amdgpu_device *adev = isp->adev; in isp_poweron()
[all …]
H A Damdgpu_isp.c1 /* SPDX-License-Identifier: MIT */
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
39 * isp_hw_init - start and test isp block
46 struct amdgpu_device *adev = ip_block->adev; in isp_hw_init()
47 struct amdgpu_isp *isp = &adev->isp; in isp_hw_init() local
49 if (isp->funcs->hw_init != NULL) in isp_hw_init()
50 return isp->funcs->hw_init(isp); in isp_hw_init()
52 return -ENODEV; in isp_hw_init()
56 * isp_hw_fini - stop the hardware block
63 struct amdgpu_isp *isp = &ip_block->adev->isp; in isp_hw_fini() local
[all …]
/linux/drivers/power/supply/
H A Disp1704_charger.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2012 - 2013 Pali Rohár <pali@kernel.org>
28 #define ISP1704_PWR_CTRL 0x3d
29 #define ISP1704_PWR_CTRL_SWCTRL (1 << 0)
38 #define NXP_VENDOR_ID 0x04cc
41 0x1704,
42 0x1707,
61 static inline int isp1704_read(struct isp1704_charger *isp, u32 reg) in isp1704_read() argument
63 return usb_phy_io_read(isp->phy, reg); in isp1704_read()
66 static inline int isp1704_write(struct isp1704_charger *isp, u32 reg, u32 val) in isp1704_write() argument
[all …]
/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsi2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI2 module
14 #include <media/v4l2-common.h>
15 #include <linux/v4l2-mediabus.h>
18 #include "isp.h"
23 * csi2_if_enable - Enable CSI2 Receiver interface.
27 static void csi2_if_enable(struct isp_device *isp, in csi2_if_enable() argument
30 struct isp_csi2_ctrl_cfg *currctrl = &csi2->ctrl; in csi2_if_enable()
32 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_CTRL, ISPCSI2_CTRL_IF_EN, in csi2_if_enable()
33 enable ? ISPCSI2_CTRL_IF_EN : 0); in csi2_if_enable()
[all …]
H A Dispccp2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CCP2 module
22 #include "isp.h"
29 #define ISPCCP2_DAT_START_MIN 0
31 #define ISPCCP2_DAT_SIZE_MIN 0
34 #define ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP 0x12
35 #define ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP 0x16
39 #define ISPCCP2_LCM_HSIZE_SKIP_MIN 0
46 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL 0
51 #define ISPCCP2_LCM_CTRL_DST_PORT_VP 0
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H A Disppreview.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP driver - Preview module
20 #include "isp.h"
26 { /* RGB-RGB Matrix */
27 {0x01E2, 0x0F30, 0x0FEE},
28 {0x0F9B, 0x01AC, 0x0FB9},
29 {0x0FE0, 0x0EC0, 0x0260}
31 {0x0000, 0x0000, 0x0000}
38 {-38, -75, 112},
39 {112, -94 , -18}
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H A Dispcsiphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
19 #include "isp.h"
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, &reg); in csiphy_routing_cfg_3630()
66 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, reg); in csiphy_routing_cfg_3630()
80 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, 0); in csiphy_routing_cfg_3430()
87 regmap_write(phy->isp->syscon, phy->isp->syscon_offset, csirxfe); in csiphy_routing_cfg_3430()
99 * and 3630, so they will not hold their contents in off-mode. This isn't an
100 * issue since the MPU power domain is forced on whilst the ISP is in use.
106 if (phy->isp->phy_type == ISP_PHY_TYPE_3630 && on) in csiphy_routing_cfg()
[all …]
H A Dispresizer.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Resizer module
18 #include "isp.h"
42 * "TRM ES3.1, table 12-46"
59 * 7-tap mode is for scale factors 0.25x to 0.5x.
60 * 4-tap mode is for scale factors 0.5x to 4.0x.
64 /* For 8-phase 4-tap horizontal filter: */
66 0x0000, 0x0100, 0x0000, 0x0000,
67 0x03FA, 0x00F6, 0x0010, 0x0000,
68 0x03F9, 0x00DB, 0x002C, 0x0000,
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/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-isp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
22 #include <media/v4l2-device.h>
24 #include "media-dev.h"
25 #include "fimc-isp-video.h"
26 #include "fimc-is-command.h"
27 #include "fimc-is-param.h"
28 #include "fimc-is-regs.h"
29 #include "fimc-is.h"
57 * fimc_isp_find_format - lookup color format by fourcc or media bus code
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H A Dfimc-is-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
14 #define REG_WDT_ISP 0x00170000
17 #define MCUCTL_BASE 0x00180000
20 #define MCUCTL_REG_MCUCTRL (MCUCTL_BASE + 0x00)
21 #define MCUCTRL_MSWRST (1 << 0)
24 #define MCUCTL_REG_BBOAR (MCUCTL_BASE + 0x04)
26 /* Interrupt Generation Register 0 from Host CPU to VIC */
27 #define MCUCTL_REG_INTGR0 (MCUCTL_BASE + 0x08)
28 /* __n = 0...9 */
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H A Dfimc-is.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
21 #include <media/videobuf2-v4l2.h>
22 #include <media/v4l2-ctrls.h>
24 #include "fimc-isp.h"
25 #include "fimc-is-command.h"
26 #include "fimc-is-sensor.h"
27 #include "fimc-is-param.h"
28 #include "fimc-is-regs.h"
30 #define FIMC_IS_DRV_NAME "exynos4-fimc-is"
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H A Dfimc-isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
20 #include <media/media-entity.h>
21 #include <media/videobuf2-v4l2.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-mediabus.h>
24 #include <media/drv-intf/exynos-fimc.h>
39 #define FIMC_ISP_SINK_WIDTH_MAX (4000 - 16)
48 #define FIMC_ISP_SD_PAD_SINK 0
55 * struct fimc_isp_frame - source/target frame properties
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/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-cpd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
9 #include <linux/dma-mapping.h>
16 #include "ipu6-bus.h"
17 #include "ipu6-cpd.h"
18 #include "ipu6-dma.h"
28 #define PKG_DIR_HDR_MARK 0x5f4955504b44525fULL
31 #define CPD_HDR_MARK 0x44504324
37 #define MAX_COMPONENT_VERSION 0xffff
39 #define MANIFEST_IDX 0
[all …]
/linux/drivers/staging/media/ipu3/
H A Dipu3-css-fw.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "ipu3-css.h"
10 #include "ipu3-css-fw.h"
11 #include "ipu3-dmamap.h"
19 bi->type, bi->blob.size, name); in imgu_css_fw_show_binary()
20 if (bi->type != IMGU_FW_ISP_FIRMWARE) in imgu_css_fw_show_binary()
23 dev_dbg(dev, " id %i mode %i bds 0x%x veceven %i/%i out_pins %i\n", in imgu_css_fw_show_binary()
24 bi->info.isp.sp.id, bi->info.isp.sp.pipeline.mode, in imgu_css_fw_show_binary()
25 bi->info.isp.sp.bds.supported_bds_factors, in imgu_css_fw_show_binary()
26 bi->info.isp.sp.enable.vf_veceven, in imgu_css_fw_show_binary()
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/linux/arch/m68k/ifpsp060/
H A Disp.doc3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
30 ------------------------------------------------
32 The file isp.sa contains the 68060 Integer Software Package.
38 isp.sa provides full emulation support for these instructions.
41 64-bit divide
42 64-bit multiply
50 --------------------
51 The file isp.sa is essentially a hexadecimal image of the
66 The source code isp.s has also been included but only for
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/linux/drivers/usb/isp1760/
H A Disp1760-core.c1 // SPDX-License-Identifier: GPL-2.0
24 #include "isp1760-core.h"
25 #include "isp1760-hcd.h"
26 #include "isp1760-regs.h"
27 #include "isp1760-udc.h"
29 static int isp1760_init_core(struct isp1760_device *isp) in isp1760_init_core() argument
31 struct isp1760_hcd *hcd = &isp->hcd; in isp1760_init_core()
32 struct isp1760_udc *udc = &isp->udc; in isp1760_init_core()
35 /* Low-level chip reset */ in isp1760_init_core()
36 if (isp->rst_gpio) { in isp1760_init_core()
[all …]
H A Disp1760-udc.c1 // SPDX-License-Identifier: GPL-2.0
22 #include "isp1760-core.h"
23 #include "isp1760-regs.h"
24 #include "isp1760-udc.h"
52 return isp1760_field_read(udc->fields, field); in isp1760_udc_read()
57 isp1760_field_write(udc->fields, field, val); in isp1760_udc_write()
64 regmap_raw_read(udc->regs, reg, &val, 4); in isp1760_udc_read_raw()
73 regmap_raw_read(udc->regs, reg, &val, 2); in isp1760_udc_read_raw16()
82 regmap_raw_write(udc->regs, reg, &val_le, 4); in isp1760_udc_write_raw()
89 regmap_raw_write(udc->regs, reg, &val_le, 2); in isp1760_udc_write_raw16()
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/linux/Documentation/devicetree/bindings/media/
H A Dti,omap3isp.txt1 OMAP 3 ISP Device Tree bindings
4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
12 ISP. The first set contains the core ISP registers up to
15 interrupts : the ISP interrupt specifier
16 iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
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H A Dallwinner,sun6i-a31-isp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-isp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 Image Signal Processor Driver (ISP)
10 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
15 - allwinner,sun6i-a31-isp
16 - allwinner,sun8i-v3s-isp
26 - description: Bus Clock
27 - description: Module Clock
[all …]
H A Dstarfive,jh7110-camss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/starfive,jh7110-camss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Starfive SoC CAMSS ISP
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
14 The Starfive CAMSS ISP is a Camera interface for Starfive JH7110 SoC. It
15 consists of a VIN controller (Video In Controller, a top-level control unit)
16 and an ISP.
[all …]
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-isp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra ISP processor
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-isp
17 - nvidia,tegra30-isp
18 - nvidia,tegra210-isp
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/linux/security/smack/
H A Dsmack_lsm.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Casey Schaufler <casey@schaufler-ca.com>
11 * Copyright (C) 2007 Casey Schaufler <casey@schaufler-ca.com>
12 * Copyright (C) 2009 Hewlett-Packard Development Company, L.P.
13 * Paul Moore <paul@paul-moore.com>
52 #define SMK_CONNECTING 0
58 * SMACK64 - for access control,
59 * SMACK64TRANSMUTE - label initialization,
60 * Not saved on files - SMACK64IPIN and SMACK64IPOUT,
61 * Must be set explicitly - SMACK64EXEC and SMACK64MMAP
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-ispcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
[all …]
H A Dsamsung,exynos4412-isp-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos4412-isp-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos4412 SoC ISP clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Clock controller for Samsung Exynos4412 SoC FIMC-ISP (Camera ISP)
[all …]
/linux/drivers/scsi/
H A Dqla1280.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 #define BIT_0 0x1
18 #define BIT_1 0x2
19 #define BIT_2 0x4
20 #define BIT_3 0x8
21 #define BIT_4 0x10
22 #define BIT_5 0x20
23 #define BIT_6 0x40
24 #define BIT_7 0x80
25 #define BIT_8 0x100
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