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/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/freebsd/sys/riscv/riscv/
H A Didentcpu.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
76 /* Supervisor-mode extension support. */
82 /* Z-extensions support. */
90 u_int isa_extensions; /* Single-letter extensions. */
98 u_int z_extensions; /* Multi-letter extensions. */
109 * Micro-architecture tables.
116 #define MARCHID_END { -1ul, NULL }
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVISAInfo.cpp1 //===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
63 "Extensions are not sorted by name"); in verifyTables()
65 "Experimental extensions are not sorted by name"); in verifyTables()
84 outs() << "All available -march extensions for RISC-V\n\n"; in printSupportedExtensions()
96 outs() << "\nExperimental extensions\n"; in printSupportedExtensions()
103 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printSupportedExtensions()
114 outs() << "\nUse -march to specify the target's extension.\n" in printSupportedExtensions()
115 "For example, clang -march=rv32i_v1p0\n"; in printSupportedExtensions()
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/freebsd/crypto/openssl/util/perl/TLSProxy/
H A DEncryptedExtensions.pm1 # Copyright 2016-2024 The OpenSSL Project Authors. All Rights Reserved.
12 use vars '@ISA';
13 push @ISA, 'TLSProxy::Message';
28 my $self = $class->SUPER::new(
40 $self->{extension_data} = "";
49 my $extensions_len = unpack('n', $self->data);
56 $extension_data = substr($self->data, 2);
62 if (length($self->data) != 2) {
67 my %extensions = ();
72 $extensions{$type} = $extdata;
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H A DCertificateRequest.pm1 # Copyright 2016-2024 The OpenSSL Project Authors. All Rights Reserved.
12 use vars '@ISA';
13 push @ISA, 'TLSProxy::Message';
28 my $self = $class->SUPER::new(
40 $self->{extension_data} = "";
50 if (TLSProxy::Proxy->is_tls13()) {
51 my $request_ctx_len = unpack('C', $self->data);
52 my $request_ctx = substr($self->data, $ptr, $request_ctx_len);
55 my $extensions_len = unpack('n', substr($self->data, $ptr));
57 my $extension_data = substr($self->data, $ptr);
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H A DCertificate.pm1 # Copyright 2016-2024 The OpenSSL Project Authors. All Rights Reserved.
12 use vars '@ISA';
13 push @ISA, 'TLSProxy::Message';
28 my $self = $class->SUPER::new(
40 $self->{first_certificate} = "";
41 $self->{extension_data} = "";
42 $self->{remaining_certdata} = "";
51 if (TLSProxy::Proxy->is_tls13()) {
52 my $context_len = unpack('C', $self->data);
53 my $context = substr($self->data, 1, $context_len);
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H A DServerHello.pm1 # Copyright 2016-2024 The OpenSSL Project Authors. All Rights Reserved.
14 use vars '@ISA';
15 push @ISA, 'TLSProxy::Message';
35 my $self = $class->SUPER::new(
47 $self->{server_version} = 0;
48 $self->{random} = [];
49 $self->{session_id_len} = 0;
50 $self->{session} = "";
51 $self->{ciphersuite} = 0;
52 $self->{comp_meth} = 0;
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H A DClientHello.pm1 # Copyright 2016-2024 The OpenSSL Project Authors. All Rights Reserved.
14 use vars '@ISA';
15 push @ISA, 'TLSProxy::Message';
30 my $self = $class->SUPER::new(
42 $self->{isdtls} = $isdtls;
43 $self->{client_version} = 0;
44 $self->{random} = [];
45 $self->{session_id_len} = 0;
46 $self->{session} = "";
47 $self->{legacy_cookie_len} = 0; #DTLS only
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/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.31 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH OPENSSL_IA32CAP 3ossl 2025-09-30 3.5.4 OpenSSL
64 OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
72 OpenSSL supports a range of x86[_64] instruction set extensions and
73 features. These extensions are denoted by individual bits or groups of bits
74 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
87 Instruction Set Extensions Programming Reference, and the AMD64 Architecture
94 .IP "bit #0+4 denoting presence of Time-Stamp Counter;" 4
95 .IX Item "bit #0+4 denoting presence of Time-Stamp Counter;"
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H A DOPENSSL_riscvcap.31 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH OPENSSL_RISCVCAP 3ossl 2025-09-30 3.5.4 OpenSSL
64 OPENSSL_riscvcap \- the RISC\-V processor capabilities vector
72 libcrypto supports RISC-V instruction set extensions. These
73 extensions are denoted by individual extension names in the capabilities
75 returned by the RISC-V Hardware Probing syscall (hwprobe) are stored
82 The environment variable is similar to the RISC-V ISA string defined in the
83 RISC-V Instruction Set Manual. It is case insensitive. Though due to the limit
96 Currently only these extensions are recognized:
104 Basic bit-manipulation
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/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVISAInfo.h1 //===-- RISCVISAInfo.h - RISC-V ISA Information -----------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
29 /// Parse RISC-V ISA info from arch string.
31 /// extensions with unrecognised versions will be silently dropped, except
32 /// for the special case of the base 'i' and 'e' extensions, where the
38 /// Parse RISC-V ISA info from an arch string that is already in normalized
44 /// Parse RISC-V ISA info from feature vector.
52 /// Convert RISC-V ISA info to a feature vector.
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DARMBuildAttributes.h1 //===-- ARMBuildAttributes.h - ARM Build Attributes -------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // ELF for the ARM Architecture r2.09 - November 30, 2012
16 //===----------------------------------------------------------------------===//
105 v6S_M = 12, // v6_M with the System extensions
106 v7E_M = 13, // v7_M with DSP extensions
116 Not_Applicable = 0, // pre v7, or cross-profile code
120 SystemProfile = (0x53) // 'S' Application or real-time profile
131 AllowThumb32 = 2, // 32-bit Thumb (implies 16-bit instructions)
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/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DMipsArchTree.cpp1 //===- MipsArchTree.cpp --------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===---------------------------------------------------------------------===//
11 //===---------------------------------------------------------------------===//
66 assert(!files.empty() && "expected non-empty file list"); in checkFlags()
73 if (config->is64 && f.flags & EF_MIPS_MICROMIPS) in checkFlags()
74 error(toString(f.file) + ": microMIPS 64-bit is not supported"); in checkFlags()
83 error(toString(f.file) + ": -mnan=" + getNanName(nan2) + in checkFlags()
84 " is incompatible with target -mnan=" + getNanName(nan)); in checkFlags()
88 error(toString(f.file) + ": -mfp" + getFpName(fp2) + in checkFlags()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRISCVTargetDefEmitter.cpp1 //===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // and RISCVISAInfo.cpp to parse the RISC-V CPUs and extensions.
12 //===----------------------------------------------------------------------===//
22 StringRef Name = R->getValueAsString("Name"); in getExtensionName()
23 Name.consume_front("experimental-"); in getExtensionName()
28 const std::vector<Record *> &Extensions, in printExtensionTable() argument
33 OS << "Extensions[] = {\n"; in printExtensionTable()
35 for (Record *R : Extensions) { in printExtensionTable()
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/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
13 OpenSSL supports a range of x86[_64] instruction set extensions and
14 features. These extensions are denoted by individual bits or groups of bits
15 stored internally as ten 32-bit capability vectors and for simplicity
16 represented logically below as five 64-bit vectors. This logical
28 Instruction Set Extensions Programming Reference, and the AMD64 Architecture
39 =item bit #0+4 denoting presence of Time-Stamp Counter;
62 =item bit #0+43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
66 =item bit #0+57 denoting AES-NI instruction set extension;
134 =item bit #128+55 denoting availability of AVX-IFMA extension;
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H A DOPENSSL_riscvcap.pod5 OPENSSL_riscvcap - the RISC-V processor capabilities vector
13 libcrypto supports RISC-V instruction set extensions. These
14 extensions are denoted by individual extension names in the capabilities
16 returned by the RISC-V Hardware Probing syscall (hwprobe) are stored
23 The environment variable is similar to the RISC-V ISA string defined in the
24 RISC-V Instruction Set Manual. It is case insensitive. Though due to the limit
35 Currently only these extensions are recognized:
47 Basic bit-manipulation
53 Carry-less multiplication
59 Single-bit instructions
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/freebsd/sys/contrib/device-tree/src/riscv/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
23 riscv,isa = "rv64imafdc";
24 riscv,isa-base = "rv64i";
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td1 //===----------------------------------------------------------------------===//
6 def ModeThumb : SubtargetFeature<"thumb-mode", "IsThumb",
10 def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",
14 //===----------------------------------------------------------------------===//
21 string TargetFeatureName, // String used for -target-feature.
32 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
38 // extension) and MVE (even in the integer-only version).
40 "Enable 16-bit FP registers",
44 "Enable 64-bit FP registers",
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/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DRISCVISAUtils.cpp1 //===-- RISCVISAUtils.cpp - RISC-V ISA Utilities --------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
19 // We rank extensions in the following order:
20 // -Single letter extensions in canonical order.
21 // -Unknown single letter extensions in alphabetical order.
22 // -Multi-letter extensions starting with 'z' sorted by canonical order of
24 // -Multi-letter extensions starting with 's' in alphabetical order.
25 // -(TODO) Multi-letter extensions starting with 'zxm' in alphabetical order.
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/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/riscv/renesas/
H A Dr9a07g043f.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
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/freebsd/crypto/openssl/util/perl/
H A Dcheckhandshake.pm2 # Copyright 2015-2018 The OpenSSL Project Authors. All Rights Reserved.
16 our @ISA = 'Exporter';
17 our @EXPORT = qw(@handmessages @extensions checkhandshake);
66 our @extensions = ();
96 # In non-TLSv1.3 we always treat reneg CH and SH like the first CH
107 if (scalar @{$proxy->message_list} > $nextmess) {
108 $message = ${$proxy->message_list}[$nextmess];
117 $chnum++ if $message->mt() == TLSProxy::Message::MT_CLIENT_HELLO;
118 $shnum++ if $message->mt() == TLSProxy::Message::MT_SERVER_HELLO;
120 next if ($message->mt() != TLSProxy::Message::MT_CLIENT_HELLO
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