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/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
34 riscv,isa:
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp1 //===- RewriteStatepointsForGC.cpp - Make GC relocations explicit ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
78 #define DEBUG_TYPE "rewrite-statepoints-for-gc"
83 static cl::opt<bool> PrintLiveSet("spp-print-liveset", cl::Hidden,
85 static cl::opt<bool> PrintLiveSetSize("spp-print-liveset-size", cl::Hidden,
88 // Print out the base pointers for debugging
89 static cl::opt<bool> PrintBasePointers("spp-print-base-pointers", cl::Hidden,
95 RematerializationThreshold("spp-rematerialization-threshold", cl::Hidden,
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp1 //==- llvm/CodeGen/SelectionDAGAddressAnalysis.cpp - DAG Address Analysis --==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
28 if (!Base.getNode() || !Other.Base.getNode()) in equalBaseIndex()
33 Off = *Other.Offset - *Offset; in equalBaseIndex()
37 if (Other.Base == Base) in equalBaseIndex()
41 if (auto *A = dyn_cast<GlobalAddressSDNode>(Base)) { in equalBaseIndex()
42 if (auto *B = dyn_cast<GlobalAddressSDNode>(Other.Base)) in equalBaseIndex()
43 if (A->getGlobal() == B->getGlobal()) { in equalBaseIndex()
44 Off += B->getOffset() - A->getOffset(); in equalBaseIndex()
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A De5500_power_isa.dtsi2 * e5500 Power ISA Device Tree Source (include)
37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
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H A De500mc_power_isa.dtsi2 * e500mc Power ISA Device Tree Source (include)
37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
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H A De6500_power_isa.dtsi2 * e6500 Power ISA Device Tree Source (include)
37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
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H A De500v1_power_isa.dtsi2 * e500v1 Power ISA Device Tree Source (include)
37 power-isa-version = "2.03";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-e.le; // Embedded.Little-Endian
43 power-isa-e.pm; // Embedded.Performance Monitor
44 power-isa-ecl; // Embedded Cache Locking
45 power-isa-mmc; // Memory Coherence
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H A De500v2_power_isa.dtsi2 * e500v2 Power ISA Device Tree Source (include)
37 power-isa-version = "2.03";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-e.le; // Embedded.Little-Endian
43 power-isa-e.pm; // Embedded.Performance Monitor
44 power-isa-ecl; // Embedded Cache Locking
45 power-isa-mmc; // Memory Coherence
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicInst.h1 //===-- llvm/IntrinsicInst.h - Intrinsic Instruction Wrappers ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // functions with the isa/dyncast family of functions. In particular, this
14 // ... MCI->getDest() ... MCI->getSource() ...
21 //===----------------------------------------------------------------------===//
46 /// This allows the standard isa/dyncast/cast functionality to work with calls
56 return getCalledFunction()->getIntrinsicID(); in getIntrinsicID()
129 /// Methods for support type inquiry through isa, cast, and dyn_cast:
131 if (const Function *CF = I->getCalledFunction()) in classof()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DLoopUnrollAnalyzer.cpp1 //===- LoopUnrollAnalyzer.cpp - Unrolling Effect Estimation -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
29 /// address (i.e. SCEVUnknown) - in this case we compute the offset and save
30 /// it along with the base address instead.
32 if (!SE.isSCEVable(I->getType())) in simplifyInstWithSCEV()
37 SimplifiedValues[I] = SC->getValue(); in simplifyInstWithSCEV()
43 if (!IterationNumber->isZero() && SE.isLoopInvariant(S, L)) in simplifyInstWithSCEV()
47 if (!AR || AR->getLoop() != L) in simplifyInstWithSCEV()
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H A DLoads.cpp1 //===- Loads.cpp - Local load analysis ------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
29 static bool isAligned(const Value *Base, const APInt &Offset, Align Alignment, in isAligned() argument
31 Align BA = Base->getPointerAlignment(DL); in isAligned()
42 assert(V->getType()->isPointerTy() && "Base must be pointer"); in isDereferenceableAndAlignedPointer()
45 if (MaxDepth-- == 0) in isDereferenceableAndAlignedPointer()
57 const Value *Base = GEP->getPointerOperand(); in isDereferenceableAndAlignedPointer() local
59 APInt Offset(DL.getIndexTypeSizeInBits(GEP->getType()), 0); in isDereferenceableAndAlignedPointer()
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H A DDelinearization.cpp1 //===---- Delinearization.cpp - MultiDimensional Index Delinearization ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // use the on-demand SCEVAddRecExpr::delinearize() function.
14 //===----------------------------------------------------------------------===//
40 return isa<UndefValue>(SU->getValue()); in containsUndefs()
57 Strides.push_back(AR->getStepRecurrence(SE)); in follow()
71 if (isa<SCEVUnknown>(S) || isa<SCEVMulExpr>(S) || in follow()
72 isa<SCEVSignExtendExpr>(S)) { in follow()
96 if (isa<SCEVAddRecExpr>(S)) { in follow()
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/freebsd/contrib/llvm-project/lldb/include/lldb/Core/
H A DEmulateInstruction.h1 //===-- EmulateInstruction.h ------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
19 #include "lldb/lldb-defines.h"
20 #include "lldb/lldb-enumerations.h"
21 #include "lldb/lldb-private-enumerations.h"
22 #include "lldb/lldb-private-types.h"
23 #include "lldb/lldb-types.h"
40 /// This class is a plug-in interface that is accessed through the standard
43 /// plug-in that supports the architecture and OS. Four callbacks and a baton
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVELaneInterleavingPass.cpp1 //===- MVELaneInterleaving.cpp - Inverleave for MVE instructions ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
77 #define DEBUG_TYPE "mve-laneinterleave"
80 "enable-mve-interleave", cl::Hidden, cl::init(true),
130 if (isa<FPExtInst>(E) || !isa<LoadInst>(E->getOperand(0))) { in isProfitableToInterleave()
136 if (T->hasOneUse() && !isa<StoreInst>(*T->user_begin())) { in isProfitableToInterleave()
145 if (!E->hasOneUse() || in isProfitableToInterleave()
146 cast<Instruction>(*E->user_begin())->getOpcode() != Instruction::Mul) { in isProfitableToInterleave()
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H A DARMParallelDSP.cpp1 //===- ARMParallelDSP.cpp - Parallel DSP Pass -----------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// Armv6 introduced instructions to perform 32-bit SIMD operations. The
12 /// DSP intrinsics, which map on these 32-bit SIMD operations.
15 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "arm-parallel-dsp"
47 DisableParallelDSP("disable-arm-parallel-dsp", cl::Hidden, cl::init(false),
51 NumLoadLimit("arm-parallel-dsp-load-limit", cl::Hidden, cl::init(16),
76 return isa<LoadInst>(LHS) && isa<LoadInst>(RHS); in HasTwoLoadInputs()
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/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DStore.cpp1 //===- Store.cpp - Interface for maps from Locations to Values ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
60 const ElementRegion *StoreManager::MakeElementRegion(const SubRegion *Base, in MakeElementRegion() argument
64 return MRMgr.getElementRegion(EleTy, idx, Base, svalBuilder.getContext()); in MakeElementRegion()
78 // Handle casts to Objective-C objects. in castRegion()
79 if (CastToTy->isObjCObjectPointerType()) in castRegion()
80 return R->StripCasts(); in castRegion()
82 if (CastToTy->isBlockPointerType()) { in castRegion()
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/freebsd/crypto/openssl/Configurations/platform/Windows/
H A DMSVC.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::Windows);
21 return platform::BASE::__concat(platform::BASE->sharedname($_[1]),
22 "-",
23 $_[0]->shlib_version_as_filename(),
25 ($_[0]->shlibvariant() // ''));
29 return platform::BASE::__concat($_[0]->staticname($_[1]), $_[0]->pdbext());
33 return platform::BASE::__concat($_[0]->sharedname($_[1]), $_[0]->pdbext());
37 return platform::BASE::__concat($_[0]->dsoname($_[1]), $_[0]->pdbext());
41 return platform::BASE::__concat($_[0]->binname($_[1]), $_[0]->pdbext());
/freebsd/crypto/openssl/Configurations/platform/
H A DWindows.pm7 use vars qw(@ISA);
9 require platform::BASE;
10 @ISA = qw(platform::BASE);
24 # Other extra that aren't defined in platform::BASE
30 # Non-installed libraries are *always* static, and their names remain
32 my $in_libname = platform::BASE->staticname($_[1]);
34 if $unified_info{attributes}->{libraries}->{$_[1]}->{noinst};
38 return platform::BASE->staticname($_[1])
49 return platform::BASE::__concat(platform::BASE->sharedname($_[1]),
50 "-",
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H A Dmingw.pm7 use vars qw(@ISA);
10 @ISA = qw(platform::Unix);
21 # Other extra that aren't defined in platform::BASE
33 return platform::BASE::__concat(platform::BASE->sharedname($_[1]),
34 "-",
35 $_[0]->shlib_version_as_filename(),
37 ? "-x64" : ""));
47 return platform::BASE::__concat(platform::BASE->sharedname($_[1]),
48 $_[0]->shlibextimport());
H A DVMS.pm7 use vars qw(@ISA);
9 require platform::BASE;
10 @ISA = qw(platform::BASE);
29 # Other extra that aren't defined in platform::BASE
34 sub opt { return $_[0]->optname($_[1]) . $_[0]->optext() }
39 # Non-installed libraries are *always* static, and their names remain
41 my $in_libname = platform::BASE->staticname($_[1]);
43 if $unified_info{attributes}->{libraries}->{$_[1]}->{noinst};
45 return platform::BASE::__concat($_[0]->osslprefix(),
46 platform::BASE->staticname($_[1]),
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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DScopeInfo.cpp1 //===--- ScopeInfo.cpp - Information about a semantic context -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
65 if (PropE->isExplicitProperty()) in getBestPropertyDecl()
66 return PropE->getExplicitProperty(); in getBestPropertyDecl()
68 return PropE->getImplicitPropertyGetter(); in getBestPropertyDecl()
73 E = E->IgnoreParenCasts(); in getBaseInfo()
78 switch (E->getStmtClass()) { in getBaseInfo()
80 D = cast<DeclRefExpr>(E)->getDecl(); in getBaseInfo()
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/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVISAInfo.h1 //===-- RISCVISAInfo.h - RISC-V ISA Information -----------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
29 /// Parse RISC-V ISA info from arch string.
32 /// for the special case of the base 'i' and 'e' extensions, where the
33 /// default version will be used (as ignoring the base is not possible).
38 /// Parse RISC-V ISA info from an arch string that is already in normalized
44 /// Parse RISC-V ISA info from feature vector.
52 /// Convert RISC-V ISA info to a feature vector.
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DGlobalDecl.h1 //===- GlobalDecl.h - Global declaration holder -----------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
44 /// GlobalDecl - represents a global declaration. This can either be a
45 /// CXXConstructorDecl and the constructor type (Base, Complete).
46 /// a CXXDestructorDecl and the destructor type (Base, Complete),
61 assert(!isa<CXXConstructorDecl>(D) && "Use other ctor with ctor decls!"); in Init()
62 assert(!isa<CXXDestructorDecl>(D) && "Use other ctor with dtor decls!"); in Init()
63 assert(!D->hasAttr<CUDAGlobalAttr>() && "Use other ctor with GPU kernels!"); in Init()
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