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/linux/Documentation/devicetree/bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
14 +-------------------------------------+
15 | Xilinx ZynqMP IPI Controller |
16 +-------------------------------------+
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/linux/arch/mips/kvm/
H A Dloongson_ipi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Loongson-3 Virtual IPI interrupt support.
53 static int loongson_vipi_read(struct loongson_kvm_ipi *ipi, in loongson_vipi_read() argument
58 uint32_t id = core + node * 4; in loongson_vipi_read() local
61 struct ipi_state *s = &(ipi->ipistate[id]); in loongson_vipi_read()
63 BUG_ON(offset & (len - 1)); in loongson_vipi_read()
67 *(uint64_t *)val = s->status; in loongson_vipi_read()
71 *(uint64_t *)val = s->en; in loongson_vipi_read()
83 pbuf = (void *)s->buf + (offset - 0x20); in loongson_vipi_read()
98 static int loongson_vipi_write(struct loongson_kvm_ipi *ipi, in loongson_vipi_write() argument
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/linux/include/linux/rpmsg/
H A Dmtk_rpmsg.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct mtk_rpmsg_info - IPI functions tied to the rpmsg device.
16 * @register_ipi: register IPI handler for an IPI id.
17 * @unregister_ipi: unregister IPI handler for a registered IPI id.
18 * @send_ipi: send IPI to an IPI id. wait is the timeout (in msecs) to wait
20 * @ns_ipi_id: the IPI id used for name service, or -1 if name service isn't
24 int (*register_ipi)(struct platform_device *pdev, u32 id,
26 void (*unregister_ipi)(struct platform_device *pdev, u32 id);
27 int (*send_ipi)(struct platform_device *pdev, u32 id,
/linux/drivers/media/platform/mediatek/vpu/
H A Dmtk_vpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
25 * enum ipi_id - the id of inter-processor interrupt
32 * For other IPI below, AP should send the request
52 * @IPI_MAX: The maximum IPI number
67 * enum rst_id - reset id to register reset function for VPU watchdog timeout
69 * @VPU_RST_ENC: encoder reset id
70 * @VPU_RST_DEC: decoder reset id
71 * @VPU_RST_MDP: MDP (Media Data Path) reset id
72 * @VPU_RST_MAX: maximum reset id
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/linux/drivers/mailbox/
H A Dzynqmp-ipi-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
8 #include <linux/arm-smccc.h>
17 #include <linux/mailbox/zynqmp-ipi-message.h>
24 /* IPI agent ID any */
27 /* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
31 /* Default IPI SMC function IDs */
40 /* IPI SMC Macros */
50 /* IPI mailbox status */
55 #define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
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/linux/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
22 /* IPI buffer MAX length */
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
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/linux/tools/testing/selftests/kvm/x86_64/
H A Dxapic_ipi_test.c1 // SPDX-License-Identifier: GPL-2.0
9 * Test that when the APIC is in xAPIC mode, a vCPU can send an IPI to wake
15 * has reentered HLT before sending the next IPI. While the vCPUs are running,
19 * Migration is a command line option. When used on non-numa machines will
20 * exit with error. Test is still usefull on non-numa for testing IPIs.
41 * Vector for IPI from sender vCPU to halting vCPU.
48 * Incremented in the IPI handler. Provides evidence to the sender that the IPI
67 * Record local version register as a cross-check that APIC access
94 data->halter_apic_id = GET_APIC_ID_FIELD(xapic_read_reg(APIC_ID)); in halter_guest_code()
95 data->halter_lvr = xapic_read_reg(APIC_LVR); in halter_guest_code()
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/linux/arch/arc/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
49 return -EINVAL; in arc_get_cpu_map()
52 return -EINVAL; in arc_get_cpu_map()
59 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
65 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
66 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
81 * - Initialise the CPU possible map early - this describes the CPUs
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/linux/drivers/irqchip/
H A Dirq-riscv-imsic-early.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
15 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-imsic-state.h"
28 struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu); in imsic_ipi_send()
30 writel_relaxed(IMSIC_IPI_ID, local->msi_va); in imsic_ipi_send()
49 /* Create IMSIC IPI multiplexing */ in imsic_ipi_domain_init()
52 return virq < 0 ? virq : -ENOMEM; in imsic_ipi_domain_init()
58 pr_info("%pfwP: providing IPIs using interrupt %d\n", imsic->fwnode, IMSIC_IPI_ID); in imsic_ipi_domain_init()
70 * instruction. If TOPEI CSR is non-zero then we translate TOPEI.ID to
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H A Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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/linux/drivers/media/platform/mediatek/vcodec/decoder/
H A Dvdec_vpu_if.c1 // SPDX-License-Identifier: GPL-2.0
15 (unsigned long)msg->ap_inst_addr; in handle_init_ack_msg()
17 mtk_vdec_debug(vpu->ctx, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr); in handle_init_ack_msg()
21 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_init_ack_msg()
22 msg->vpu_inst_addr); in handle_init_ack_msg()
23 vpu->inst_addr = msg->vpu_inst_addr; in handle_init_ack_msg()
25 mtk_vdec_debug(vpu->ctx, "- vpu_inst_addr = 0x%x", vpu->inst_addr); in handle_init_ack_msg()
28 vpu->fw_abi_version = 0; in handle_init_ack_msg()
30 * Instance ID is only used if ABI version >= 2. Initialize it with in handle_init_ack_msg()
33 vpu->inst_id = 0xdeadbeef; in handle_init_ack_msg()
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H A Dvdec_ipi_msg.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * enum vdec_ipi_msgid - message id between AP and VPU
12 * @AP_IPIMSG_XXX : AP to VPU cmd message id
13 * @VPU_IPIMSG_XXX_ACK : VPU ack AP cmd message id
36 * struct vdec_ap_ipi_cmd - generic AP to VPU ipi command format
39 * @inst_id : instance ID. Used if the ABI version >= 2.
54 * struct vdec_vpu_ipi_ack - generic VPU to AP ipi command format
66 * struct vdec_ap_ipi_init - for AP_IPIMSG_DEC_INIT
78 * struct vdec_ap_ipi_dec_start - for AP_IPIMSG_DEC_START
81 * @inst_id : instance ID. Used if the ABI version >= 2.
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H A Dvdec_vpu_if.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * struct vdec_vpu_inst - VPU instance for video codec
14 * @id : ipi msg id for each decoder
15 * @core_id : core id used to separate different hardware
21 * @inst_id : if fw_abi_version >= 2, contains the instance ID to be given
23 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
26 * @handler : ipi handler for each decoder
32 int id; member
49 * vpu_dec_init - init decoder instance and allocate required resource in VPU.
56 * vpu_dec_start - start decoding, basically the function will be invoked once
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/linux/arch/powerpc/include/asm/
H A Dmpic.h1 /* SPDX-License-Identifier: GPL-2.0 */
71 * Per-Processor registers
92 * Per-source registers
149 * Per-Processor registers
162 * Per-source registers
284 /* vector numbers used for internal sources (ipi/timers) */
344 * The top 4 bits contain an MPIC bhw id that is used to index the
346 * Note setting any ID (leaving those bits to 0) means standard MPIC
355 /* Set this for a big-endian MPIC */
359 /* Broken IPI registers (autodetected) */
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/linux/arch/x86/hyperv/
H A Dhv_apic.c1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V specific APIC code.
45 static void hv_apic_icr_write(u32 low, u32 id) in hv_apic_icr_write() argument
49 reg_val = SET_XAPIC_DEST_FIELD(id); in hv_apic_icr_write()
93 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) in hv_apic_eoi_write()
105 * IPI implementation on Hyper-V.
124 ipi_arg->vector = vector; in __send_ipi_mask_ex()
125 ipi_arg->reserved = 0; in __send_ipi_mask_ex()
126 ipi_arg->vp_set.valid_bank_mask = 0; in __send_ipi_mask_ex()
130 * when the IPI is sent to all currently present CPUs. in __send_ipi_mask_ex()
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/linux/arch/powerpc/kvm/
H A Dbook3s_xive.h1 /* SPDX-License-Identifier: GPL-2.0-only */
24 * pass-through but it's easier to keep around as the same
25 * guest interrupt can alternatively be emulated or pass-through
36 u32 ipi_number; /* XIVE IPI HW number */
37 struct xive_irq_data ipi_data; /* XIVE IPI associated data */
38 u32 pt_number; /* XIVE Pass-through number if any */
39 struct xive_irq_data *pt_data; /* XIVE Pass-through associated data */
53 bool lsi; /* level-sensitive interrupt */
66 /* Select the "right" interrupt (IPI vs. passthrough) */
71 if (state->pt_number) { in kvmppc_xive_select_irq()
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/linux/Documentation/virt/kvm/x86/
H A Dhypercalls.rst1 .. SPDX-License-Identifier: GPL-2.0
8 KVM Hypercalls have a three-byte sequence of either the vmcall or the vmmcall
18 R2-R7 are used for parameters 1-6. In addition, R1 is used for hypercall
25 refer to Documentation/virt/kvm/s390/s390-diag.rst.
28 It uses R3-R10 and hypercall number in R11. R4-R11 are used as output registers.
31 KVM hypercalls uses 4 byte opcode, that are patched with 'hypercall-instructions'
33 For more information refer to Documentation/virt/kvm/ppc-pv.rst
37 number in $2 (v0). Up to four arguments may be placed in $4-$7 (a0-a3) and
50 ------------------------
58 ----------------
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/linux/Documentation/virt/kvm/devices/
H A Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
20 interrupt server numbers (ie, highest possible vcpu id plus one).
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
51 Zero is the highest priority, 255 means no IPI is pending.
54 Zero means no interrupt pending, 2 means an IPI is pending
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/linux/arch/sparc/kernel/
H A Dsmp_32.c1 // SPDX-License-Identifier: GPL-2.0
56 void smp_store_cpu_info(int id) in smp_store_cpu_info() argument
61 cpu_data(id).udelay_val = loops_per_jiffy; in smp_store_cpu_info()
63 cpu_find_by_mid(id, &cpu_node); in smp_store_cpu_info()
64 cpu_data(id).clock_tick = prom_getintdefault(cpu_node, in smp_store_cpu_info()
65 "clock-frequency", 0); in smp_store_cpu_info()
66 cpu_data(id).prom_node = cpu_node; in smp_store_cpu_info()
70 printk(KERN_NOTICE "No MID found for CPU%d at node 0x%08x", id, cpu_node); in smp_store_cpu_info()
73 cpu_data(id).mid = mid; in smp_store_cpu_info()
126 * CPU model dependent way of implementing IPI generation targeting in arch_smp_send_reschedule()
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/linux/arch/xtensa/include/asm/
H A Dmxregs.h8 * Copyright (C) 2008 - 2013 Tensilica Inc.
21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
24 * 0190 0...0x..x 8-bit IPI partition register
26 * V (10-bit) Release/Version
27 * P ( 4-bit) Number of cores - 1
28 * U (18-bit) ID
29 * 01a0 i.......i 32-bit ConfigID
/linux/arch/xtensa/kernel/
H A Dsmp.c8 * Copyright (C) 2008 - 2013 Tensilica Inc.
53 /* IPI (Inter Process Interrupt) */
62 if (request_irq(irq, ipi_interrupt, IRQF_PERCPU, "ipi", NULL)) in ipi_init()
63 pr_err("Failed to request irq %u (ipi)\n", irq); in ipi_init()
75 /* Bits 0...18 of SYSCFGID contain the core id */ in get_core_id()
95 pr_info("%s: Core Id = %d\n", __func__, core_id); in smp_init_cpus()
117 static int boot_secondary_processors = 1; /* Set with xt-gdb via .xt-gdb */
146 current->active_mm = mm; in secondary_start_kernel()
174 pr_debug("%s: cpu: %d, run_stall_mask: %lx ---> %lx\n", in mx_cpu_start()
184 pr_debug("%s: cpu: %d, run_stall_mask: %lx ---> %lx\n", in mx_cpu_stop()
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/linux/arch/arm64/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SMP initialisation and IPI support
27 #include <linux/irqchip/arm-gic-v3.h>
56 #include <trace/events/ipi.h>
98 return -ENOSYS; in op_cpu_kill()
111 if (ops->cpu_boot) in boot_secondary()
112 return ops->cpu_boot(cpu); in boot_secondary()
114 return -EOPNOTSUPP; in boot_secondary()
134 if (ret != -EPERM) in __cpu_up()
170 pr_crit("CPU%u: does not support 52-bit VAs\n", cpu); in __cpu_up()
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/linux/Documentation/devicetree/bindings/power/reset/
H A Dxlnx,zynqmp-power.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 The zynqmp-power node describes the power management configurations.
18 const: xlnx,zynqmp-power
28 that will be the phandle to the intended sub-mailbox
34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
37 - description: tx channel
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/linux/arch/powerpc/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and
66 #include <trace/events/ipi.h>
117 * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to
118 * the set its siblings that share the L1-cache.
123 * On some big-cores system, thread_group_l2_cache_map for each CPU
125 * L2-cache.
150 /* Special case - we inhibit secondary thread startup in smp_generic_cpu_bootable()
169 return -EINVAL; in smp_generic_kick_cpu()
173 * cpu_start field to become non-zero After we set cpu_start, in smp_generic_kick_cpu()
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/linux/arch/powerpc/sysdev/xics/
H A Dicp-native.c1 // SPDX-License-Identifier: GPL-2.0-or-later
58 return in_be32(&icp_native_regs[cpu]->xirr.word); in icp_native_get_xirr()
65 out_be32(&icp_native_regs[cpu]->xirr.word, value); in icp_native_set_xirr()
72 out_8(&icp_native_regs[cpu]->xirr.bytes[0], value); in icp_native_set_cppr()
77 out_8(&icp_native_regs[n_cpu]->qirr.bytes[0], value); in icp_native_set_qirr()
99 /* Clear any pending IPI */ in icp_native_teardown_cpu()
105 /* We take the ipi irq but and never return so we in icp_native_flush_ipi()
106 * need to EOI the IPI, but want to leave our priority 0 in icp_native_flush_ipi()
161 * include a full barrier before causing the IPI. in icp_native_cause_ipi_rm()
163 xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys; in icp_native_cause_ipi_rm()
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