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/linux/drivers/clk/imx/
H A Dclk-imx27.c40 "ahb", "ipg", "per1_div", "per2_div",
70 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
73 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
99 clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); in _mx27_clocks_init()
100 clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); in _mx27_clocks_init()
101 clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); in _mx27_clocks_init()
102 clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); in _mx27_clocks_init()
103 clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); in _mx27_clocks_init()
104 clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); in _mx27_clocks_init()
105 clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); in _mx27_clocks_init()
[all …]
H A Dclk-imx25.c49 "ipg", "dummy", "dummy", "dummy",
54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
156 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2); in __mx25_clocks_init()
157 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3); in __mx25_clocks_init()
158 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4); in __mx25_clocks_init()
159 clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5); in __mx25_clocks_init()
160 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6); in __mx25_clocks_init()
161 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7); in __mx25_clocks_init()
162 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8); in __mx25_clocks_init()
[all …]
H A Dclk-imx35.c65 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, enumerator
132 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx35_clocks_init()
164 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); in _mx35_clocks_init()
165 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); in _mx35_clocks_init()
166 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); in _mx35_clocks_init()
167 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); in _mx35_clocks_init()
168 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); in _mx35_clocks_init()
169 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); in _mx35_clocks_init()
170 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); in _mx35_clocks_init()
171 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); in _mx35_clocks_init()
[all …]
H A Dclk-imx5.c73 static const char *per_root_sel[] = { "per_podf", "ipg", };
96 static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
101 "ipg", "per_root", "ckil", "dummy",};
153 clk[IMX5_CLK_SPBA] = imx_clk_gate2_flags("spba", "ipg", MXC_CCM_CCGR5, 0, CLK_IS_CRITICAL); in mx5_clocks_common_init()
154 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); in mx5_clocks_common_init()
187 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); in mx5_clocks_common_init()
188 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); in mx5_clocks_common_init()
190 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); in mx5_clocks_common_init()
192 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); in mx5_clocks_common_init()
196 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); in mx5_clocks_common_init()
[all …]
H A Dclk-imx31.c34 static const char *per_sel[] = { "per_div", "ipg", };
39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
65 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
80 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); in _mx31_clocks_init()
81 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); in _mx31_clocks_init()
83 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); in _mx31_clocks_init()
84 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); in _mx31_clocks_init()
95 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); in _mx31_clocks_init()
96 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); in _mx31_clocks_init()
101 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); in _mx31_clocks_init()
[all …]
H A Dclk-imx6ul.c56 static const char *perclk_sels[] = { "ipg", "osc", };
65 "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
306 hws[IMX6UL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); in imx6ul_clocks_init()
356 hws[IMX6UL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12); in imx6ul_clocks_init()
359 hws[IMX6UL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x68, 12); in imx6ul_clocks_init()
362 hws[IMX6UL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14); in imx6ul_clocks_init()
364 hws[IMX6UL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18); in imx6ul_clocks_init()
368 hws[IMX6UL_CLK_UART2_IPG] = imx_clk_hw_gate2("uart2_ipg", "ipg", base + 0x68, 28); in imx6ul_clocks_init()
372 hws[IMX6UL_CLK_GPIO2] = imx_clk_hw_gate2("gpio2", "ipg", base + 0x68, 30); in imx6ul_clocks_init()
379 hws[IMX6UL_CLK_ADC2] = imx_clk_hw_gate2("adc2", "ipg", base + 0x6c, 8); in imx6ul_clocks_init()
[all …]
H A Dclk-imx6sll.c50 static const char *perclk_sels[] = { "ipg", "osc", };
223 hws[IMX6SLL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); in imx6sll_clocks_init()
263 hws[IMX6SLL_CLK_UART2_IPG] = imx_clk_hw_gate2("uart2_ipg", "ipg", base + 0x68, 28); in imx6sll_clocks_init()
265 hws[IMX6SLL_CLK_GPIO2] = imx_clk_hw_gate2("gpio2", "ipg", base + 0x68, 30); in imx6sll_clocks_init()
272 hws[IMX6SLL_CLK_UART3_IPG] = imx_clk_hw_gate2("uart3_ipg", "ipg", base + 0x6c, 10); in imx6sll_clocks_init()
278 hws[IMX6SLL_CLK_UART4_IPG] = imx_clk_hw_gate2("uart4_ipg", "ipg", base + 0x6c, 24); in imx6sll_clocks_init()
280 hws[IMX6SLL_CLK_GPIO1] = imx_clk_hw_gate2("gpio1", "ipg", base + 0x6c, 26); in imx6sll_clocks_init()
281 hws[IMX6SLL_CLK_GPIO5] = imx_clk_hw_gate2("gpio5", "ipg", base + 0x6c, 30); in imx6sll_clocks_init()
284 hws[IMX6SLL_CLK_GPIO6] = imx_clk_hw_gate2("gpio6", "ipg", base + 0x70, 0); in imx6sll_clocks_init()
289 hws[IMX6SLL_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12); in imx6sll_clocks_init()
[all …]
H A Dclk-imx6sl.c47 static const char *perclk_sels[] = { "ipg", "osc", };
112 * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
116 * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
332 …hws[IMX6SL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", b… in imx6sl_clocks_init()
373 …hws[IMX6SL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, … in imx6sl_clocks_init()
383 …hws[IMX6SL_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, … in imx6sl_clocks_init()
390 …hws[IMX6SL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, … in imx6sl_clocks_init()
391 …hws[IMX6SL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2("mmdc_p1_ipg", "ipg", base + 0x74, … in imx6sl_clocks_init()
397 …hws[IMX6SL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ipg", base + 0x7c, … in imx6sl_clocks_init()
398 …hws[IMX6SL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, … in imx6sl_clocks_init()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25.dtsi106 clock-names = "ipg";
117 clock-names = "ipg";
127 clock-names = "ipg", "per";
136 clock-names = "ipg", "per";
145 clock-names = "ipg", "per";
154 clock-names = "ipg", "per";
164 clock-names = "ipg";
185 clock-names = "ipg", "per";
224 clock-names = "ipg", "per";
233 clock-names = "ipg", "per";
[all …]
H A Dimx27.dtsi97 clock-names = "ipg", "ahb";
115 clock-names = "ipg", "per";
124 clock-names = "ipg", "per";
133 clock-names = "ipg", "per";
143 clock-names = "ipg", "per";
152 clock-names = "ref", "ipg";
176 clock-names = "ipg", "per";
186 clock-names = "ipg", "per";
196 clock-names = "ipg", "per";
206 clock-names = "ipg", "per";
[all …]
H A Dimx31.dtsi106 clock-names = "ipg", "per";
115 clock-names = "ipg", "per";
134 clock-names = "ipg", "per";
154 clock-names = "ipg", "per";
164 clock-names = "ipg", "per";
181 clock-names = "ipg", "per";
192 clock-names = "ipg", "per";
203 clock-names = "ipg", "per";
212 clock-names = "ipg", "per";
247 clock-names = "ipg", "per";
[all …]
H A Dimx1.dtsi84 clock-names = "ipg", "per";
93 clock-names = "ipg", "per";
103 clock-names = "ipg", "ahb", "per";
113 clock-names = "ipg", "per";
123 clock-names = "ipg", "per";
134 clock-names = "ipg", "per";
143 clock-names = "ipg", "ahb";
153 clock-names = "ipg", "per";
173 clock-names = "ipg", "per";
195 clock-names = "ipg", "per";
H A Dimx7s.dtsi475 clock-names = "ipg", "per";
484 clock-names = "ipg", "per";
494 clock-names = "ipg", "per";
504 clock-names = "ipg", "per";
745 clock-names = "ipg", "per";
785 clock-names = "ipg", "per";
796 clock-names = "ipg", "per";
807 clock-names = "ipg", "per";
818 clock-names = "ipg", "per";
922 clock-names = "ipg", "per";
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi68 clock-names = "ipg";
164 clock-names = "ipg", "ips", "sys", "ref", "mclk";
176 clock-names = "ipg", "ips", "sys", "ref", "mclk";
187 clock-names = "ipg", "per";
197 clock-names = "ipg";
207 clock-names = "ipg";
217 clock-names = "ipg";
230 clock-names = "ipg";
238 clock-names = "ipg";
250 clock-names = "ipg", "ips", "sys", "ref", "mclk";
[all …]
H A Dmpc5125twr.dts134 clock-names = "ipg", "ips", "sys", "ref", "mclk";
146 clock-names = "ipg", "ips", "sys", "ref", "mclk";
155 clock-names = "ipg", "per";
165 clock-names = "ipg";
175 clock-names = "ipg";
185 clock-names = "ipg";
198 clock-names = "ipg";
241 clock-names = "ipg";
263 clock-names = "ipg", "mclk";
275 clock-names = "ipg", "mclk";
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dtestmode.c190 mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode) in mt7915_tm_set_ipg_params() argument
205 if (ipg < sig_ext + slot_time + sifs) in mt7915_tm_set_ipg_params()
206 ipg = 0; in mt7915_tm_set_ipg_params()
208 if (!ipg) in mt7915_tm_set_ipg_params()
211 ipg -= sig_ext; in mt7915_tm_set_ipg_params()
213 if (ipg <= (TM_MAX_SIFS + slot_time)) { in mt7915_tm_set_ipg_params()
214 sifs = ipg - slot_time; in mt7915_tm_set_ipg_params()
216 u32 val = (ipg + slot_time) / slot_time; in mt7915_tm_set_ipg_params()
224 ipg -= ((1 << cw) - 1) * slot_time; in mt7915_tm_set_ipg_params()
226 aifsn = ipg / slot_time; in mt7915_tm_set_ipg_params()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-dma.dtsi11 dma_ipg_clk: clock-dma-ipg {
33 clock-names = "per", "ipg";
51 clock-names = "per", "ipg";
69 clock-names = "per", "ipg";
87 clock-names = "per", "ipg";
101 clock-names = "ipg", "baud";
115 clock-names = "ipg", "baud";
129 clock-names = "ipg", "baud";
143 clock-names = "ipg", "baud";
158 clock-names = "ipg", "per";
[all …]
H A Dimx95.dtsi682 clock-names = "per", "ipg";
696 clock-names = "per", "ipg";
712 clock-names = "per", "ipg";
726 clock-names = "per", "ipg";
738 clock-names = "ipg";
750 clock-names = "ipg";
762 clock-names = "ipg";
774 clock-names = "ipg";
786 clock-names = "ipg", "per";
800 clock-names = "ipg", "per";
[all …]
H A Dimx8-ss-cm40.dtsi9 cm40_ipg_clk: clock-cm40-ipg {
28 clock-names = "ipg", "baud";
41 clock-names = "per", "ipg";
63 clock-names = "ipg";
/linux/drivers/clocksource/
H A Dtimer-imx-tpm.c185 struct clk *ipg; in tpm_timer_init() local
188 ipg = of_clk_get_by_name(np, "ipg"); in tpm_timer_init()
189 if (IS_ERR(ipg)) { in tpm_timer_init()
190 pr_err("tpm: failed to get ipg clk\n"); in tpm_timer_init()
194 ret = clk_prepare_enable(ipg); in tpm_timer_init()
196 pr_err("tpm: ipg clock enable failed (%d)\n", ret); in tpm_timer_init()
197 clk_put(ipg); in tpm_timer_init()
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi104 clock-names = "ipg", "per";
113 clock-names = "ipg";
124 clock-names = "ipg";
135 clock-names = "ipg";
146 clock-names = "ipg";
282 clock-names = "ipg";
408 clock-names = "ipg";
422 clock-names = "ipg";
510 clock-names = "ipg";
519 clock-names = "ipg";
[all …]
/linux/drivers/net/ethernet/mscc/
H A Docelot_police.h15 MSCC_QOS_RATE_MODE_LINE, /* Measure line rate in kbps incl. IPG */
16 MSCC_QOS_RATE_MODE_DATA, /* Measures data rate in kbps excl. IPG */
31 u8 ipg; /* Size of IPG when MSCC_QOS_RATE_MODE_LINE is chosen */ member
H A Docelot_police.c11 #define POL_MODE_LINERATE 0 /* Incl IPG. Unit: 33 1/3 kbps, 4096 bytes */
12 #define POL_MODE_DATARATE 1 /* Excl IPG. Unit: 33 1/3 kbps, 4096 bytes */
30 u8 ipg = 20; in qos_policer_conf_set() local
41 ipg = min_t(u8, GENMASK(4, 0), conf->ipg); in qos_policer_conf_set()
132 value = (ANA_POL_MODE_CFG_IPG_SIZE(ipg) | in qos_policer_conf_set()
/linux/sound/soc/fsl/
H A Dfsl_rpmsg.c244 rpmsg->ipg = devm_clk_get_optional(&pdev->dev, "ipg"); in fsl_rpmsg_probe()
245 if (IS_ERR(rpmsg->ipg)) in fsl_rpmsg_probe()
246 return PTR_ERR(rpmsg->ipg); in fsl_rpmsg_probe()
294 ret = clk_prepare_enable(rpmsg->ipg); in fsl_rpmsg_runtime_resume()
296 dev_err(dev, "failed to enable ipg clock: %d\n", ret); in fsl_rpmsg_runtime_resume()
309 clk_disable_unprepare(rpmsg->ipg); in fsl_rpmsg_runtime_resume()
319 clk_disable_unprepare(rpmsg->ipg); in fsl_rpmsg_runtime_suspend()
/linux/Documentation/devicetree/bindings/display/
H A Dfsl,tcon.txt8 - clocks: From common clock binding: handle to tcon ipg clock.
9 - clock-names: From common clock binding: Shall be "ipg".
16 clock-names = "ipg";

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