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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
42 the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
44 - iommu-map-mask: A mask to be applied to each Requester ID prior to being
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/freebsd/sys/arm64/iommu/
H A Diommu.c54 #include <dev/iommu/busdma_iommu.h>
63 #include "iommu.h"
66 static MALLOC_DEFINE(M_IOMMU, "IOMMU", "IOMMU framework");
77 struct iommu_unit *iommu; member
86 struct iommu_unit *iommu; in iommu_domain_unmap_buf() local
89 iommu = iodom->iommu; in iommu_domain_unmap_buf()
90 error = IOMMU_UNMAP(iommu->dev, iodom, entry->start, entry->end - in iommu_domain_unmap_buf()
99 struct iommu_unit *iommu; in iommu_domain_map_buf() local
113 iommu = iodom->iommu; in iommu_domain_map_buf()
114 error = IOMMU_MAP(iommu->dev, iodom, va, ma, entry->end - in iommu_domain_map_buf()
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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
36 1:1 mapping from IOMMU to memory.
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
43 The meaning of the IOMMU specifier is defined by the device tree binding of
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H A Dqcom,iommu.txt1 * QCOM IOMMU v1 Implementation
4 a similar looking IOMMU but without access to the global register space,
12 "qcom,msm8916-iommu"
13 "qcom,msm8953-iommu"
15 Followed by "qcom,msm-iommu-v1".
28 - #iommu-cells : Must be 1. Index identifies the context-bank #.
30 - ranges : Base address and size of the iommu context banks.
32 - qcom,iommu-secure-id : secure-id.
38 - "qcom,msm-iommu-v1-ns" : non-secure context bank
39 - "qcom,msm-iommu-v1-sec" : secure context bank
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H A Dqcom,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
14 a similar looking IOMMU, but without access to the global register space
23 - qcom,msm8916-iommu
24 - qcom,msm8953-iommu
25 - const: qcom,msm-iommu-v1
28 - qcom,msm8953-iommu
29 - qcom,msm8976-iommu
30 - const: qcom,msm-iommu-v2
34 - description: Clock required for IOMMU register group access
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H A Dti,omap-iommu.txt1 OMAP2+ IOMMU
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
16 Documentation/devicetree/bindings/iommu/iommu.txt
21 - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
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H A Dmsm,iommu-v0.txt1 * QCOM IOMMU
3 The MSM IOMMU is an implementation compatible with the ARM VMSA short
5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
27 required for iommu's register accesses.
29 required by iommu for bus accesses.
31 Each bus master connected to an IOMMU must reference the IOMMU in its device
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H A Dsprd,iommu.yaml5 $id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
8 title: Unisoc IOMMU and Multi-media MMU
16 - sprd,iommu-v1
18 "#iommu-cells":
21 Unisoc IOMMUs are all single-master IOMMU devices, therefore no
24 Documentation/devicetree/bindings/iommu/iommu.txt
37 - "#iommu-cells"
43 iommu_disp: iommu@63000800 {
44 compatible = "sprd,iommu-v1";
46 #iommu-cells = <0>;
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H A Drockchip,iommu.txt1 Rockchip IOMMU
4 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
9 - compatible : Should be "rockchip,iommu"
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - interrupt-names : Interrupt name for the IOMMU instance
13 - #iommu-cells : Should be <0>. This indicates the iommu is a
16 Documentation/devicetree/bindings/iommu/iommu.txt
17 - clocks : A list of clocks required for the IOMMU to be accessible by
30 vopl_mmu: iommu@ff940300 {
31 compatible = "rockchip,iommu";
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H A Dallwinner,sun50i-h6-iommu.yaml4 $id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml#
7 title: Allwinner H6 IOMMU
14 "#iommu-cells":
21 - const: allwinner,sun50i-h6-iommu
22 - const: allwinner,sun50i-h616-iommu
24 - const: allwinner,sun55i-a523-iommu
25 - const: allwinner,sun50i-h616-iommu
40 - "#iommu-cells"
57 iommu: iommu@30f0000 {
58 compatible = "allwinner,sun50i-h6-iommu";
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H A Drockchip,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
7 title: Rockchip IOMMU
13 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
17 For information on assigning IOMMU controller to its peripheral devices,
18 see generic IOMMU bindings.
24 - rockchip,iommu
25 - rockchip,rk3568-iommu
28 - rockchip,rk3588-iommu
29 - const: rockchip,rk3568-iommu
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H A Dapple,dart.yaml4 $id: http://devicetree.org/schemas/iommu/apple,dart.yaml#
7 title: Apple DART IOMMU
20 This DART IOMMU also raises interrupts in response to various
39 Reference to the gate clock phandle if required for this IOMMU.
42 '#iommu-cells':
46 a master to the IOMMU.
54 - '#iommu-cells'
61 dart1: iommu@82f80000 {
65 #iommu-cells = <1>;
73 dart2a: iommu
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H A Dqcom,apq8064-iommu.yaml5 $id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
8 title: Qualcomm APQ8064 IOMMU
14 The MSM IOMMU is an implementation compatible with the ARM VMSA short
16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
20 const: qcom,apq8064-iommu
42 "#iommu-cells":
44 description: Each IOMMU specifier describes a single Stream ID.
48 description: The total number of context banks in the IOMMU.
67 iommu@7500000 {
68 compatible = "qcom,apq8064-iommu";
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H A Dmediatek,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
7 title: MediaTek IOMMU Architecture Implementation
80 - mediatek,mt8186-iommu-mm # generation two
81 - mediatek,mt8188-iommu-vdo # generation two
82 - mediatek,mt8188-iommu-vpp # generation two
83 - mediatek,mt8188-iommu-infra # generation two
85 - mediatek,mt8195-iommu-vdo # generation two
86 - mediatek,mt8195-iommu-vpp # generation two
87 - mediatek,mt8195-iommu
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H A Dxen,grant-dma.yaml4 $id: http://devicetree.org/schemas/iommu/xen,grant-dma.yaml#
7 title: Xen specific IOMMU for virtualized devices (e.g. virtio)
13 The Xen IOMMU represents the Xen grant table interface. Grant mappings
14 are to be used with devices connected to the Xen IOMMU using the "iommus"
22 '#iommu-cells':
30 - "#iommu-cells"
36 iommu {
38 #iommu-cells = <1>;
/freebsd/sys/contrib/device-tree/Bindings/virtio/
H A Diommu.txt1 * virtio IOMMU PCI device
3 When virtio-iommu uses the PCI transport, its programming interface is
5 device tree statically describes the relation between IOMMU and DMA
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
7 contains a child node representing the IOMMU device explicitly.
11 - compatible: Should be "virtio,pci-iommu"
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
18 - #iommu-cells: Each platform DMA master managed by the IOMMU is assigned
20 For virtio-iommu, #iommu-cells must be 1.
24 - DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
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H A Dpci-iommu.yaml4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
7 title: virtio-iommu device using the virtio-pci transport
13 When virtio-iommu uses the PCI transport, its programming interface is
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
17 contains a child node representing the IOMMU device explicitly.
19 DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
20 virtio-iommu node doesn't have an "iommus" property, and is omitted from
21 the iommu-map property of the root complex.
30 - const: virtio,pci-iommu
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H A Dmmio.txt11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
21 - iommus: If the device accesses memory through an IOMMU, it should
22 have an "iommus" property [1]. Since virtio-iommu itself
23 does not access memory through an IOMMU, the "virtio,mmio"
24 node cannot have both an "#iommu-cells" and an "iommus"
38 viommu: iommu@3100 {
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmediatek-vcodec.txt25 - iommus : should point to the respective IOMMU block with master port as
26 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
52 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
53 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
54 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
55 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
56 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
57 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
58 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
59 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
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H A Dmediatek,vcodec-encoder.yaml53 List of the hardware port in respective IOMMU block for current Socs.
54 Refer to bindings/iommu/mediatek,iommu.yaml.
150 iommus = <&iommu M4U_PORT_VENC_RCPU>,
151 <&iommu M4U_PORT_VENC_REC>,
152 <&iommu M4U_PORT_VENC_BSDMA>,
153 <&iommu M4U_PORT_VENC_SV_COMV>,
154 <&iommu M4U_PORT_VENC_RD_COMV>,
155 <&iommu M4U_PORT_VENC_CUR_LUMA>,
156 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
157 <&iommu M4U_PORT_VENC_REF_LUMA>,
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/freebsd/sys/x86/iommu/
H A Damd_cmd.c56 #include <dev/iommu/busdma_iommu.h>
57 #include <x86/iommu/amd_reg.h>
58 #include <x86/iommu/x86_iommu.h>
59 #include <x86/iommu/amd_iommu.h>
81 amdiommu_enable_qi_intr(struct iommu_unit *iommu) in amdiommu_enable_qi_intr() argument
85 unit = IOMMU2AMD(iommu); in amdiommu_enable_qi_intr()
94 amdiommu_disable_qi_intr(struct iommu_unit *iommu) in amdiommu_disable_qi_intr() argument
98 unit = IOMMU2AMD(iommu); in amdiommu_disable_qi_intr()
105 amdiommu_cmd_advance_tail(struct iommu_unit *iommu) in amdiommu_cmd_advance_tail() argument
109 unit = IOMMU2AMD(iommu); in amdiommu_cmd_advance_tail()
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H A Damd_drv.c68 #include <dev/iommu/iommu.h>
69 #include <x86/iommu/amd_reg.h>
70 #include <x86/iommu/x86_iommu.h>
71 #include <x86/iommu/amd_iommu.h>
76 * All enumerated AMD IOMMU units.
241 if (bus_get_domain(sc->iommu.dev, &dom) == 0) in amdiommu_create_dev_tbl()
315 msi_count = pci_msi_count(sc->iommu.dev); in amdiommu_setup_intr()
316 msix_count = pci_msix_count(sc->iommu.dev); in amdiommu_setup_intr()
318 device_printf(sc->iommu.dev, "needs MSI-class intr\n"); in amdiommu_setup_intr()
326 * one IOMMU unit per function, and uses MSI. in amdiommu_setup_intr()
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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dfsl,qoriq-mc.txt21 between ICIDs and IOMMUs, so an iommu-map property is used to define
23 an IOMMU.
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
29 Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
117 - iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier
121 (icid-base,iommu,iommu-base,length).
124 associated with the listed IOMMU, with the iommu-specifier
125 (i - icid-base + iommu-base).
151 smmu: iommu@5000000 {
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H A Dfsl,qoriq-mc.yaml31 between ICIDs and IOMMUs, so an iommu-map property is used to define
33 an IOMMU.
35 For generic IOMMU bindings, see
36 Documentation/devicetree/bindings/iommu/iommu.txt.
39 Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
90 iommu-map:
92 Maps an ICID to an IOMMU and associated iommu-specifier
96 (icid-base,iommu,iommu-base,length).
99 associated with the listed IOMMU, with the iommu-specifier
100 (i - icid-base + iommu-base).
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/freebsd/sys/conf/
H A Dfiles.x86156 dev/iommu/busdma_iommu.c optional acpi iommu pci
157 dev/iommu/iommu_gas.c optional acpi iommu pci
347 x86/iommu/amd_cmd.c optional acpi iommu pci
348 x86/iommu/amd_ctx.c optional acpi iommu pci
349 x86/iommu/amd_drv.c optional acpi iommu pci
350 x86/iommu/amd_event.c optional acpi iommu pci
351 x86/iommu/amd_idpgtbl.c optional acpi iommu pci
352 x86/iommu/amd_intrmap.c optional acpi iommu pci
353 x86/iommu/intel_ctx.c optional acpi iommu pci
354 x86/iommu/intel_drv.c optional acpi iommu pci
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