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/linux/drivers/gpu/drm/msm/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
22 struct msm_mmu *parent; member
35 /* based on iommu_pgsize() in iommu.c: */
46 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
62 pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0); in calc_pgsize()
73 if ((iova ^ paddr) & (pgsize_next - 1)) in calc_pgsize()
77 offset = pgsize_next - (addr_merge & (pgsize_next - 1)); in calc_pgsize()
95 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; in msm_iommu_pagetable_unmap()
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/linux/drivers/iommu/
H A Diommu-sysfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU sysfs class support
10 #include <linux/iommu.h>
16 * As devices are added to the IOMMU, we'll add links to the group.
38 .name = "iommu",
50 * Init the struct device for the IOMMU. IOMMU specific attributes can
52 * IOMMU type.
54 int iommu_device_sysfs_add(struct iommu_device *iommu, in iommu_device_sysfs_add() argument
55 struct device *parent, in iommu_device_sysfs_add() argument
62 iommu->dev = kzalloc(sizeof(*iommu->dev), GFP_KERNEL); in iommu_device_sysfs_add()
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/linux/arch/powerpc/platforms/cell/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * IOMMU implementation for Cell Broadband Processor Architecture
5 * (C) Copyright IBM Corporation 2006-2008
24 #include <asm/iommu.h>
26 #include <asm/pci-bridge.h>
29 #include <asm/cell-regs.h>
34 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
43 * once spider-net has been fixed to pass the correct direction
89 #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */
90 #define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */
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/linux/arch/arm64/boot/dts/apple/
H A Dt600x-die0.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
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H A Dt8112.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
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H A Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/iommu/
H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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H A Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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H A Dsamsung,sysmmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17 System MMU is an IOMMU and supports identical translation table format to
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
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/linux/arch/powerpc/boot/dts/fsl/
H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dt2081si-post.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
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/linux/drivers/iommu/intel/
H A Dnested.c1 // SPDX-License-Identifier: GPL-2.0
3 * nested.c - nested mode translation support
14 #include <linux/iommu.h>
16 #include <linux/pci-ats.h>
18 #include "iommu.h"
26 struct intel_iommu *iommu = info->iommu; in intel_nested_attach_dev() local
30 if (info->domain) in intel_nested_attach_dev()
33 if (iommu->agaw < dmar_domain->s2_domain->agaw) { in intel_nested_attach_dev()
35 return -ENODEV; in intel_nested_attach_dev()
39 * Stage-1 domain cannot work alone, it is nested on a s2_domain. in intel_nested_attach_dev()
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H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2014 Intel Corporation.
17 #include <linux/dma-direct.h>
21 #include <linux/pci-ats.h>
27 #include "iommu.h"
28 #include "../dma-iommu.h"
30 #include "../iommu-pages.h"
38 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
39 #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
40 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
46 #address-cells = <1>;
47 #size-cells = <0>;
49 cpu-map {
62 compatible = "arm,cortex-a15";
65 clock-names = "cpu";
66 operating-points-v2 = <&cpu0_opp_table>;
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/linux/drivers/acpi/arm64/
H A Diort.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/iommu.h>
21 #include <linux/dma-map-ops.h>
45 * iort_set_fwnode() - Create iort_fwnode and use it to register
46 * iommu data in the iort_fwnode_list
48 * @iort_node: IORT table node associated with the IOMMU
62 return -ENOMEM; in iort_set_fwnode()
64 INIT_LIST_HEAD(&np->list); in iort_set_fwnode()
65 np->iort_node = iort_node; in iort_set_fwnode()
66 np->fwnode = fwnode; in iort_set_fwnode()
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/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,vcodec-subdev-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
16 parent and child device node.
20 +------------------------------------------------+-------------------------------------+
22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------||-------------------+---------------------||--------------+
25 || lat || | core workqueue <parent>
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/linux/drivers/vfio/
H A Dvfio_iommu_type1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
14 * VT-d, but that makes it harder to re-use as theoretically anyone
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userspace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
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/linux/include/linux/
H A Diommu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
30 * if the IOMMU page table format is equivalent.
57 * struct iommu_fault_page_request - Page Request data
67 * @private_data: device-specific private information
82 * struct iommu_fault - Generic fault data
92 * enum iommu_page_response_code - Return status of fault handlers
107 * struct iommu_page_response - Generic page response information
140 * struct iopf_queue - IO Page Fault queue
151 /* iommu fault flags */
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