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/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <tjeznach@rivosinc.com>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
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H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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H A Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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H A Dsamsung,sysmmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17 System MMU is an IOMMU and supports identical translation table format to
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
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/linux/drivers/gpu/drm/msm/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
29 struct msm_mmu *parent; member
45 /* based on iommu_pgsize() in iommu.c: */
56 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
72 pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0); in calc_pgsize()
83 if ((iova ^ paddr) & (pgsize_next - 1)) in calc_pgsize()
87 offset = pgsize_next - (addr_merge & (pgsize_next - 1)); in calc_pgsize()
105 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; in msm_iommu_pagetable_unmap()
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/linux/Documentation/userspace-api/
H A Diommufd.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 IOMMUFD is the user API to control the IOMMU subsystem as it relates to managing
16 drivers are eventually expected to deprecate any internal IOMMU logic
20 I/O page tables for all IOMMUs, with room in the design to add non-generic
24 small letter (iommufd) refers to the file descriptors created via /dev/iommu for
31 --------------------
35 - IOMMUFD_OBJ_IOAS, representing an I/O address space (IOAS), allowing map/unmap
41 - IOMMUFD_OBJ_DEVICE, representing a device that is bound to iommufd by an
44 - IOMMUFD_OBJ_HWPT_PAGING, representing an actual hardware I/O page table
45 (i.e. a single struct iommu_domain) managed by the iommu driver. "PAGING"
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/linux/drivers/acpi/riscv/
H A Drimt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2024-2025, Ventana Micro Systems Inc
12 #include <linux/iommu.h>
34 * rimt_set_fwnode() - Create rimt_fwnode and use it to register
35 * iommu data in the rimt_fwnode_list
37 * @rimt_node: RIMT table node associated with the IOMMU
51 return -ENOMEM; in rimt_set_fwnode()
53 INIT_LIST_HEAD(&np->list); in rimt_set_fwnode()
54 np->rimt_node = rimt_node; in rimt_set_fwnode()
55 np->fwnode = fwnode; in rimt_set_fwnode()
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/linux/arch/powerpc/boot/dts/fsl/
H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dt2081si-post.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
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H A Dt1040si-post.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
35 #include <dt-bindings/thermal/thermal.h>
38 compatible = "fsl,bman-fbpr";
39 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,qman-fqd";
44 alloc-ranges = <0 0 0x10000 0>;
48 compatible = "fsl,qman-pfdr";
49 alloc-ranges = <0 0 0x10000 0>;
53 #address-cells = <2>;
54 #size-cells = <1>;
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/linux/drivers/iommu/intel/
H A Dnested.c1 // SPDX-License-Identifier: GPL-2.0
3 * nested.c - nested mode translation support
14 #include <linux/iommu.h>
16 #include <linux/pci-ats.h>
18 #include "iommu.h"
26 struct intel_iommu *iommu = info->iommu; in intel_nested_attach_dev() local
32 if (iommu->agaw < dmar_domain->s2_domain->agaw) { in intel_nested_attach_dev()
34 return -ENODEV; in intel_nested_attach_dev()
38 * Stage-1 domain cannot work alone, it is nested on a s2_domain. in intel_nested_attach_dev()
40 * to ensure the s2_domain is compatible with this IOMMU. in intel_nested_attach_dev()
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H A Dirq_remapping.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
13 #include <linux/irqchip/irq-msi-lib.h>
22 #include <asm/pci-direct.h>
25 #include "iommu.h"
27 #include "../iommu-pages.h"
30 struct intel_iommu *iommu; member
37 struct intel_iommu *iommu; member
44 struct intel_iommu *iommu; member
69 * ->dmar_global_lock
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/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/linux/drivers/acpi/arm64/
H A Diort.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/iommu.h>
21 #include <linux/dma-map-ops.h>
45 * iort_set_fwnode() - Create iort_fwnode and use it to register
46 * iommu data in the iort_fwnode_list
48 * @iort_node: IORT table node associated with the IOMMU
62 return -ENOMEM; in iort_set_fwnode()
64 INIT_LIST_HEAD(&np->list); in iort_set_fwnode()
65 np->iort_node = iort_node; in iort_set_fwnode()
66 np->fwnode = fwnode; in iort_set_fwnode()
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos4.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
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/linux/Documentation/devicetree/bindings/pci/
H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
26 the standard "reset-gpios" and "max-link-speed" properties appear on
38 - items:
39 - enum:
40 - apple,t8103-pcie
41 - apple,t8112-pcie
42 - apple,t6000-pcie
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/linux/drivers/vfio/
H A Dvfio_iommu_type1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
14 * VT-d, but that makes it harder to re-use as theoretically anyone
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userspace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
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/linux/arch/arm64/boot/dts/arm/
H A Dmorello-sdp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
6 /dts-v1/;
11 compatible = "arm,morello-sdp", "arm,morello";
18 stdout-path = "serial0:115200n8";
21 dpu_aclk: clock-350000000 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <350000000>;
26 clock-output-names = "aclk";
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/linux/Documentation/driver-api/
H A Dvfio-mediated-device.rst1 .. SPDX-License-Identifier: GPL-2.0-only
17 The number of use cases for virtualizing DMA devices that do not have built-in
25 an IOMMU/device-agnostic framework for exposing direct device access to user
26 space in a secure, IOMMU-protected environment. This framework is used for
37 * Add a mediated device to and remove it from an IOMMU group
44 The following high-level block diagram shows the main components and interfaces
48 +---------------+
50 | +-----------+ | mdev_register_driver() +--------------+
51 | | | +<------------------------+ |
53 | | bus | +------------------------>+ vfio_mdev.ko |<-> VFIO user
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