Home
last modified time | relevance | path

Searched +full:invert +full:- +full:enable (Results 1 – 25 of 216) sorted by relevance

123456789

/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
H A Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jef
[all...]
/freebsd/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,fimd.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,s3c2443-fimd
19 - samsung,s3c6400-fimd
20 - samsung,s5pv210-fimd
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dautoidle.txt7 or fixed-factor.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - reg : offset for the register controlling the autoidle
13 - ti,autoidle-shift : bit shift of the autoidle enable bit
14 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
18 #clock-cells = <0>;
19 compatible = "ti,divider-clock";
21 ti,max-div = <31>;
22 ti,autoidle-shift = <8>;
24 ti,index-starts-at-one;
[all …]
H A Dfixed-factor-clock.txt6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
20 - reg: offset for the autoidle register of this clock, see [2]
21 - ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dqcom,q6dsp-lpass-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 - qcom,q6afe-dais
20 '#sound-dai-cells':
23 '#address-cells':
26 '#size-cells':
31 '^dai@[0-9]+$':
[all …]
H A Dcs35l36.txt5 - compatible : "cirrus,cs35l36"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
18 - cirrus,boost-pea
[all...]
H A Dcirrus,cs35l41.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - david.rhodes@cirrus.com
19 - cirrus,cs35l40
20 - cirrus,cs35l41
28 '#sound-dai-cells':
33 reset-gpios:
36 VA-supply:
39 VP-supply:
[all …]
H A Dcirrus,cs42l43.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 - $ref: dai-common.yaml#
26 - cirrus,cs42l43
31 vdd-p-supply:
35 vdd-a-supply:
39 vdd-d-supply:
43 vdd-io-supply:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dnxp,pca9685-pwm.txt1 NXP PCA9685 16-channel 12-bit PWM LED controller
5 - compatible: "nxp,pca9685-pwm"
6 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
12 - invert (bool): boolean to enable inverted logic
13 - open-drain (bool): boolean to configure outputs with open-drain structure;
14 if omitted use totem-pole structure
22 compatible = "nxp,pca9685-pwm";
23 #pwm-cells = <2>;
25 invert;
26 open-drain;
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpio
[all...]
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.txt4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
13 - "aotag"
[all …]
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210-p2530.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 stdout-path = "serial0:115200n8";
24 /delete-property/ dmas;
25 /delete-property/ dma-names;
31 clock-frequency = <400000>;
35 nvidia,invert-interrup
[all...]
/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dsamsung-fimd.txt1 Device-Tree bindings for Samsung SoC display controller (FIMD)
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14 "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
15 "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
17 - reg: physical base address and length of the FIMD registers set.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dst,sti-irq-syscfg.txt2 -----------------------------------------------------------
9 - compatible : Should be "st,stih407-irq-syscfg"
10 - st,syscfg : Phandle to Cortex-A9 IRQ system config registers
11 - st,irq-device : Array of IRQs to enable - should be 2 in length
12 - st,fiq-device : Array of FIQs to enable - should be 2 in length
15 - st,invert-ext : External IRQs can be inverted at will. This property inverts
23 irq-syscfg {
24 compatible = "st,stih407-irq-syscfg";
26 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
28 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
/freebsd/sys/contrib/device-tree/Bindings/iio/addac/
H A Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/usr.sbin/pwm/
H A Dpwm.862 .Bl -tag -width "-f device"
81 Enable the PWM channel.
85 Invert PWM signal polarity
88 .Bl -bullet
91 .Bd -literal
92 pwm -f /dev/pwm/pwmc0.1 -C
96 and enable the channel:
97 .Bd -literal
98 pwm -f pwmc1.1 -E -p 50000 -d 25000
106 .Bd -literal
[all …]
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dfsl-imx-uart.txt4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
11 - fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached
13 respectively, and that the peripheral should invert its output/input
15 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
16 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
18 properties. In case you use "uart-has-rtscts" the signal that controls
[all …]
/freebsd/sys/dev/hwpmc/
H A Dhwpmc_core.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
73 * Fixed-function counters.
86 * 63 - 45 Reserved (do not touch)
88 * 43 - 41 Reserved (do not touch)
90 * 39 - 37 Reserved (do not touch)
92 * 35 - 33 Reserved (do not touch)
96 * 13-12 Ctr 3 Enable
99 * 9-8 Ctr 2 Enable
102 * 5-4 Ctr 1 Enable
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_pwm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2017 Poul-Henning Kamp <phk@FreeBSD.org>
49 {"broadcom,bcm2835-pwm", 1},
50 {"brcm,bcm2835-pwm", 1},
73 bus_space_write_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off, _val)
75 bus_space_read_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off)
77 bus_space_write_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off, _val)
79 bus_space_read_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off)
103 (void)bcm2835_clkman_set_frequency(sc->clkman, BCM_PWM_CLKSRC, 0); in bcm_pwm_reconf()
[all …]
/freebsd/sys/dev/qcom_qup/
H A Dqcom_spi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
69 { "qcom,spi-qup-v1.1.1", QCOM_SPI_HW_QPI_V1_1 },
70 { "qcom,spi-qup-v2.1.1", QCOM_SPI_HW_QPI_V2_1 },
71 { "qcom,spi-qup-v2.2.1", QCOM_SPI_HW_QPI_V2_2 },
84 bool invert = !! (cs & SPIBUS_CS_HIGH); in qcom_spi_set_chipsel() local
88 if (sc->cs_pins[cs] == NULL) { in qcom_spi_set_chipsel()
89 device_printf(sc->sc_dev, in qcom_spi_set_chipsel()
90 "%s: cs=%u, active=%u, invert=%u, no gpio?\n", in qcom_spi_set_chipsel()
91 __func__, cs, active, invert); in qcom_spi_set_chipsel()
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dcurrituck.dts11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
[all …]
/freebsd/share/man/man4/
H A Dpwmc.435 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
49 driver provides device-control access to a channel of PWM hardware.
84 .Bl -tag -width indent
99 .Bd -literal
104 bool enable;
107 .Bl -tag -width period
109 The duration, in nanoseconds, of one complete on-off cycle.
113 Flags that affect the output signal can be bitwise-ORed together.
116 .Bl -tag -width PWM_POLARITY_INVERTED -compact
[all …]
/freebsd/sys/arm/allwinner/
H A Daw_cir.c1 /*-
49 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r))
50 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v))
54 /* Global Enable */
56 /* RX enable */
58 /* CIR mode enable */
63 /* Pulse Polarity Invert flag */
83 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1))
99 /* Bit 15 - value (pulse/space) */
101 /* Bits 0:14 - sample duration */
[all …]

123456789