| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gt_types.h | 110 /* Serialize global tlb invalidations */
114 * Batch TLB invalidations
119 * so we track how many TLB invalidations have been
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| /linux/Documentation/arch/x86/ |
| H A D | tlb.rst | 41 You may be doing too many individual invalidations if you see the
43 profiles. If you believe that individual invalidations being
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| /linux/arch/powerpc/include/asm/ |
| H A D | mmu_context.h | 135 * in order to force TLB invalidations to be global as to in mm_context_add_copro()
159 * for the time being. Invalidations will remain global if in mm_context_remove_copro()
161 * it could make some invalidations local with no flush in mm_context_remove_copro()
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| H A D | mmu.h | 76 /* Enable use of broadcast TLB invalidations. We don't always set it
78 * use of such invalidations
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| /linux/arch/sh/mm/ |
| H A D | cache-shx3.c | 39 * Broadcast I-cache block invalidations by default. in shx3_cache_init()
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| /linux/arch/openrisc/include/asm/ |
| H A D | cacheflush.h | 29 * invalidations need to be broadcasted to all other cpu in the system in
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| /linux/drivers/gpu/drm/xe/ |
| H A D | Kconfig.debug | 105 are hit during checks for userptr invalidations.
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | l2_cache.json | 12 …h return data even if the snoops cause an invalidation. L2 cache line invalidations which do not w…
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| H A D | l1d_cache.json | 12 …nce operations. The following cache operations are not counted:\n\n1. Invalidations which do not r…
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | l2_cache.json | 12 …h return data even if the snoops cause an invalidation. L2 cache line invalidations which do not w…
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| H A D | l1d_cache.json | 12 …nce operations. The following cache operations are not counted:\n\n1. Invalidations which do not r…
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | l2_cache.json | 12 "PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line invalidations which do not write data outside the CPU and snoops which return data from an L1 cache are not counted. Data would not be written outside the cache when invalidating a clean cache line."
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| H A D | l1d_cache.json | 12 "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode."
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| /linux/include/uapi/rdma/ |
| H A D | rdma_user_ioctl.h | 80 /* read TID cache invalidations */
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| /linux/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_clflush.c | 99 * flushed/invalidated. As we always have to emit invalidations in i915_gem_clflush_object()
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| /linux/drivers/iommu/intel/ |
| H A D | pasid.c | 316 * - Flush the caches per Table 28 ”Guidance to Software for Invalidations“
622 * From VT-d spec table 25 "Guidance to Software for Invalidations": in intel_pasid_setup_dirty_tracking()
1119 * Cache invalidations after change in a context table entry that was present
1120 * according to the Spec 6.5.3.3 (Guidance to Software for Invalidations). If
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| H A D | cache.json | 39 … which return data, regardless of whether they cause an invalidation. Invalidations from the L2 wh…
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,cci-400.yaml | 15 and manage coherency, TLB invalidations and memory barriers.
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| /linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| H A D | mmu.h | 148 struct mutex mutex; /* serialises mmu invalidations */
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| /linux/drivers/infiniband/hw/mlx5/ |
| H A D | odp.c | 268 u64 invalidations = 0; in mlx5_ib_invalidate_range() local
295 * overwrite the same MTTs. Concurent invalidations might race us, in mlx5_ib_invalidate_range()
313 /* Count page invalidations */ in mlx5_ib_invalidate_range()
314 invalidations += idx - blk_start_idx + 1; in mlx5_ib_invalidate_range()
333 mlx5_update_odp_stats_with_handled(mr, invalidations, invalidations); in mlx5_ib_invalidate_range()
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| /linux/drivers/misc/cxl/ |
| H A D | cxllib.c | 123 * However, we'll turn the invalidations off, so that in cxllib_switch_phb_mode()
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| /linux/Documentation/mm/ |
| H A D | hmm.rst | 116 specific commands in it to perform the update (unmap, cache invalidations, and
357 handles CPU page table invalidations so the device driver only has to
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| /linux/include/linux/ |
| H A D | migrate.h | 212 * callbacks to avoid device MMU invalidations for device private
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cmn/sys/ |
| H A D | cmn.json | 54 "BriefDescription": "Counts number of SF eviction cache invalidations initiated.",
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| /linux/fs/xfs/scrub/ |
| H A D | reap.c | 170 * of buffer invalidations to 2048.
441 * buffer invalidations, so we need to return early so that we can in xreap_agextent_iter()
1196 * transaction is full of logged buffer invalidations, so we need to in xrep_reap_bmapi_iter()
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