| /freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynos9810-pinctrl.dtsi | 16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 interrupt-parent = <&gic>;
34 #interrupt-cells = <2>;
41 interrupt-controller;
42 interrupt-parent = <&gic>;
51 #interrupt-cells = <2>;
58 interrupt-controller;
59 interrupt-parent = <&gic>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | renesas,rzv2h-icu.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml#
7 title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit
14 - $ref: /schemas/interrupt-controller.yaml#
17 The Interrupt Control Unit (ICU) handles external interrupts (NMI, IRQ, and
27 '#interrupt-cells':
29 PORT_IRQ[0-15] interrupt, as per user manual. The second cell is used to
36 interrupt-controller: true
44 - description: NMI interrupt
45 - description: PORT_IRQ0 interrupt
46 - description: PORT_IRQ1 interrupt
[all …]
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| H A D | renesas,rzg2l-irqc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
14 IA55 performs various interrupt controls including synchronization for the external
16 interrupts output by each IP. And it notifies the interrupt to the GIC
18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
35 '#interrupt-cells':
37 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
44 interrupt-controller: true
52 - description: NMI interrupt
53 - description: IRQ0 interrupt
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| H A D | ti,c64x+megamod-pic.txt | 1 C6X Interrupt Chips
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
14 - #interrupt-cells: <1>
16 Interrupt Specifier Definition
18 Single cell specifying the core interrupt priority level (4-15) where
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
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| H A D | fsl,imx8qxp-dc-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
7 title: Freescale i.MX8qxp Display Controller interrupt controller
10 The Display Controller has a built-in interrupt controller with the following
18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
20 allowing it to use a global interrupt controller instead.
22 Each interrupt can be protected against SW running in user mode. In that case,
23 only privileged AHB access can control the interrupt status.
38 interrupt-controller: true
40 "#interrupt-cells":
45 - description: store9 shadow load interrupt(blit engine)
[all …]
|
| H A D | interrupts.txt | 1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
[all …]
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| H A D | samsung,exynos4210-combiner.txt | 1 * Samsung Exynos Interrupt Combiner Controller
3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
4 can combine interrupt sources as a group and provide a single interrupt request
5 for the group. The interrupt request from each group are connected to a parent
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
9 interrupt sources can be connected to a combiner. The combiner outputs one
10 combined interrupt for its eight interrupt sources. The combined interrupt
11 is usually connected to a parent interrupt controller.
13 A single node in the device tree is used to describe the interrupt combiner
[all …]
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| H A D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
[all …]
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| H A D | mrvl,intc.txt | 1 * Marvell MMP Interrupt controller
8 - reg : Address and length of the register set of the interrupt controller.
9 If the interrupt controller is intc, address and length means the range
10 of the whole interrupt controller. The "marvell,mmp3-intc" controller
11 also has a secondary range for the second CPU core. If the interrupt
14 interrupt controller.
15 - reg-names : Name of the register set of the interrupt controller. It's
16 only required in mux-intc interrupt controller.
17 - interrupts : Should be the port interrupt shared by mux interrupts. It's
18 only required in mux-intc interrupt controller.
[all …]
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| H A D | samsung,exynos4210-combiner.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
19 interrupt sources can be connected to a combiner. The combiner outputs one
20 combined interrupt for its eight interrupt sources. The combined interrupt is
21 usually connected to a parent interrupt controller.
[all …]
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| H A D | brcm,bcm7120-l2-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
22 directly output an interrupt signal towards the interrupt controller parent,
23 or if they will output an interrupt signal at this 2nd level interrupt
30 - not all bits within the interrupt controller actually map to an interrupt
34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
36 0 -----[ MUX ] ------------|==========> GIC interrupt 75
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| H A D | marvell,orion-intc.txt | 1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
18 intc: interrupt-controller {
20 interrupt-controller;
21 #interrupt-cells = <1>;
26 * Bridge interrupt controller
[all …]
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| /freebsd/share/man/man9/ |
| H A D | intr_event.9 | 40 .Nd "kernel interrupt handler and thread API"
78 The interrupt event API provides methods to manage the registration and
79 execution of interrupt handlers and their associated thread contexts.
81 Each interrupt event in the system corresponds to a single hardware or software
82 interrupt source.
83 Each interrupt event maintains a list of interrupt handlers, sorted by
85 An interrupt event will typically, but not always, have an associated
87 known as the interrupt thread.
91 An interrupt handler contains two distinct handler functions:
98 function is run from interrupt context and is intended to perform quick
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
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| /freebsd/sys/contrib/device-tree/Bindings/net/wireless/ |
| H A D | qcom,ath11k.yaml | 32 interrupt-names:
111 - description: misc-pulse1 interrupt events
112 - description: misc-latch interrupt events
113 - description: sw exception interrupt events
114 - description: watchdog interrupt events
115 - description: interrupt event for ring CE0
116 - description: interrupt event for ring CE1
117 - description: interrupt event for ring CE2
118 - description: interrupt event for ring CE3
119 - description: interrupt event for ring CE4
[all …]
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| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | fsp2.dts | 64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
[all …]
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| /freebsd/sys/contrib/device-tree/src/mips/brcm/ |
| H A D | bcm7358.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
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| H A D | bcm7360.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
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| H A D | bcm7346.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| H A D | bcm7362.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
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| H A D | bcm7435.dtsi | 42 cpu_intc: interrupt-controller {
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
47 #interrupt-cells = <1>;
71 periph_intc: interrupt-controller@41b500 {
76 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&cpu_intc>;
83 sun_l2_intc: interrupt-controller@403000 {
86 interrupt-controller;
[all …]
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| /freebsd/sys/contrib/device-tree/src/mips/loongson/ |
| H A D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
25 interrupt-parent = <&pic>;
33 interrupt-parent = <&pic>;
43 interrupt-parent = <&pic>;
53 interrupt-parent = <&pic>;
63 interrupt-parent = <&pic>;
89 interrupt-parent = <&pic>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/loongarch/ |
| H A D | loongson-2k2000.dtsi | 8 #include <dt-bindings/interrupt-controller/irq.h>
41 cpuintc: interrupt-controller {
42 compatible = "loongson,cpu-interrupt-controller";
43 #interrupt-cells = <1>;
44 interrupt-controller;
96 interrupt-parent = <&eiointc>;
119 interrupt-parent = <&liointc>;
124 liointc: interrupt-controller@1fe01400 {
128 interrupt-controller;
129 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos5410-pinctrl.dtsi | 16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/crypto/ |
| H A D | hisilicon,hip06-sec.yaml | 41 - description: SEC unit error queue interrupt
42 - description: Completion interrupt for queue 0
43 - description: Error interrupt for queue 0
44 - description: Completion interrupt for queue 1
45 - description: Error interrupt for queue 1
46 - description: Completion interrupt for queue 2
47 - description: Error interrupt for queue 2
48 - description: Completion interrupt for queue 3
49 - description: Error interrupt for queue 3
50 - description: Completion interrupt for queue 4
[all …]
|