| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | x-powers,axp152.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/x-powers,axp152.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: X-Powers AXP PMIC
10 - Chen-Yu Tsai <wens@csie.org>
13 - if:
18 - x-powers,axp152
19 - x-powers,axp202
20 - x-powers,axp209
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | msr.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
24 4-byte alignment physical address of a memory area which must be
42 An odd version indicates an in-progress update.
53 Note that although MSRs are per-CPU entities, the effect of this
63 4-byte aligned physical address of a memory area which must be in
80 updates of this structure is arbitrary and implementation-dependent.
89 An odd version indicates an in-progress update.
104 tsc-related quantity to nanoseconds
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| /linux/Documentation/devicetree/bindings/net/nfc/ |
| H A D | st,st-nci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/nfc/st,st-nci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - st,st21nfcb-i2c
16 - st,st21nfcb-spi
17 - st,st21nfcc-i2c
19 reset-gpios:
22 ese-present:
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| H A D | st,st21nfca.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: st,st21nfca-i2c
16 enable-gpios:
19 ese-present:
30 uicc-present:
37 - compatible
38 - enable-gpios
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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| H A D | brcm,bcm7038-l1-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
10 This block is a first level interrupt controller that is typically connected
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
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| H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
17 attached to every HLIC namely software interrupts, the timer interrupt, and
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| H A D | apple,aic2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller 2
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller 2 is a simple interrupt controller present on
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
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| /linux/Documentation/devicetree/bindings/iio/addac/ |
| H A D | adi,ad74115.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
33 spi-cpol: true
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | atmel-usb.txt | 6 - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
8 - reg: Address and length of the register set for the device
9 - interrupts: Should contain ohci interrupt
10 - clocks: Should reference the peripheral, host and system clocks
11 - clock-names: Should contain three strings
15 - num-ports: Number of ports.
16 - atmel,vbus-gpio: If present, specifies a gpio that needs to be
18 - atmel,oc-gpio: If present, specifies a gpio that needs to be
22 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
25 clock-names = "ohci_clk", "hclk", "uhpck";
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| /linux/Documentation/devicetree/bindings/ata/ |
| H A D | pata-arasan.txt | 4 - compatible: "arasan,cf-spear1340"
5 - reg: Address range of the CF registers
6 - interrupt: Should contain the CF interrupt number
7 - clock-frequency: Interface clock rate, in Hz, one of
21 - arasan,broken-udma: if present, UDMA mode is unusable
22 - arasan,broken-mwdma: if present, MWDMA mode is unusable
23 - arasan,broken-pio: if present, PIO mode is unusable
24 - dmas: one DMA channel, as described in bindings/dma/dma.txt
26 - dma-names: the corresponding channel name, must be "data"
31 compatible = "arasan,cf-spear1340";
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| /linux/arch/openrisc/include/asm/ |
| H A D | spr_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
141 #define SPR_VR_UVRP 0x00000040 /* Updated Version Registers Present */
154 * Bit definitions for the Unit Present Register
157 #define SPR_UPR_UP 0x00000001 /* UPR present */
158 #define SPR_UPR_DCP 0x00000002 /* Data cache present */
159 #define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
160 #define SPR_UPR_DMP 0x00000008 /* Data MMU present */
161 #define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
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| /linux/drivers/iommu/ |
| H A D | msm_iommu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
8 #include <linux/interrupt.h>
28 * be present. These mappings are typically determined at design time and are
33 /* Maximum number of context banks that can be present in IOMMU */
37 * struct msm_iommu_dev - a single IOMMU hardware instance
38 * ncb Number of context banks present on this IOMMU HW instance
40 * irq: Interrupt number
64 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
68 * bank, terminated by -1. The MID is a set of signals on the
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-thunderx.txt | 1 Cavium ThunderX/OCTEON-TX GPIO controller bindings
4 - reg: The controller bus address.
5 - gpio-controller: Marks the device node as a GPIO controller.
6 - #gpio-cells: Must be 2.
7 - First cell is the GPIO pin number relative to the controller.
8 - Second cell is a standard generic flag bitfield as described in gpio.txt.
11 - compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used.
12 - interrupt-controller: Marks the device node as an interrupt controller.
13 - #interrupt-cells: Must be present and have value of 2 if
14 "interrupt-controller" is present.
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| H A D | gpio-grgpio.txt | 10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
22 no irq for that line. Driver provides no interrupt support if not
23 present.
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | fsl-tsec-phy.txt | 5 the definition of the PHY node in booting-without-of.txt for an example
9 - reg : Offset and length of the register set for the device, and optionally
14 - compatible : Should define the compatible device type for the
16 - "fsl,gianfar-tbi"
17 - "fsl,gianfar-mdio"
18 - "fsl,etsec2-tbi"
19 - "fsl,etsec2-mdio"
20 - "fsl,ucc-mdio"
21 - "fsl,fman-mdio"
23 - "gianfar"
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| H A D | mediatek-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | st-rc.txt | 1 Device-Tree bindings for ST IRB IP
4 - compatible: Should contain "st,comms-irb".
5 - reg: Base physical address of the controller and length of memory
7 - interrupts: interrupt-specifier for the sole interrupt generated by
8 the device. The interrupt specifier format depends on the interrupt
10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
11 protocol used for receiving remote control signals. rx-mode should
12 be present iff the rx pins are wired up.
13 - tx-mode: should be "infrared". This property specifies the L1
14 protocol used for transmitting remote control signals. tx-mode should
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| /linux/drivers/comedi/drivers/ |
| H A D | amplc_dio200_pci.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
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| /linux/Documentation/devicetree/bindings/arm/tegra/ |
| H A D | nvidia,tegra186-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci.txt | 3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
6 And for the interrupt mapping part:
8 Open Firmware Recommended Practice: Interrupt Mapping
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
15 If present this property assigns a fixed PCI domain number to a host bridge,
21 - max-link-speed:
22 If present this property specifies PCI gen for link capability. Host
27 - reset-gpios:
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| /linux/drivers/irqchip/ |
| H A D | irq-sifive-plic.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "riscv-plic: " fmt
9 #include <linux/interrupt.h>
25 * This driver implements a version of the RISC-V PLIC with the actual layout
28 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
30 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
31 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
39 * Each interrupt source has a priority register associated with it.
46 * Each hart context has a vector of interrupt enable bits associated with it.
47 * There's one bit for each interrupt source.
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| /linux/Documentation/devicetree/bindings/net/can/ |
| H A D | mpc5xxx-mscan.txt | 2 ------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
7 fsl,mpc5200-mscan nodes
8 -----------------------
9 In addition to the required compatible-, reg- and interrupt-properties, you can
12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
16 present.
18 fsl,mpc5121-mscan nodes
19 -----------------------
20 In addition to the required compatible-, reg- and interrupt-properties, you can
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| /linux/drivers/gpu/drm/lima/ |
| H A D | lima_pmu.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
11 #define pmu_write(reg, data) writel(data, ip->iomem + reg)
12 #define pmu_read(reg) readl(ip->iomem + reg)
16 struct lima_device *dev = ip->dev; in lima_pmu_wait_cmd()
20 err = readl_poll_timeout(ip->iomem + LIMA_PMU_INT_RAWSTAT, in lima_pmu_wait_cmd()
24 dev_err(dev->dev, "%s timeout wait pmu cmd\n", in lima_pmu_wait_cmd()
35 struct lima_device *dev = ip->dev; in lima_pmu_get_ip_mask()
41 if (dev->id == lima_gpu_mali400) { in lima_pmu_get_ip_mask()
44 if (dev->ip[lima_ip_pp0 + i].present) in lima_pmu_get_ip_mask()
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| /linux/Documentation/devicetree/bindings/input/touchscreen/ |
| H A D | zinitix,bt400.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 are Korea-produced touchscreens with embedded microcontrollers. The
11 BT4xx series was produced 2010-2013 and the BT5xx series 2013-2014.
14 - Michael Srba <Michael.Srba@seznam.cz>
15 - Linus Walleij <linus.walleij@linaro.org>
18 - $ref: touchscreen.yaml#
19 - $ref: ../input.yaml#
27 - zinitix,bt402
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