/freebsd/sys/contrib/device-tree/Bindings/mfd/ |
H A D | x-powers,axp152.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mfd/x-powers,axp152.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: X-Powers AXP PMIC 10 - Chen-Yu Tsai <wens@csie.org> 13 - if: 18 - x-powers,axp152 19 - x-powers,axp202 20 - x-powers,axp209 [all …]
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H A D | stericsson,ab8500.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ST-Ericsson Analog Baseband AB8500 and AB8505 10 - Linus Walleij <linus.walleij@linaro.org> 13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit 14 handling power management (regulators), analog-to-digital conversion 15 (ADC), battery charging, fuel gauging of the battery, battery-backed 16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms 21 USB charging handling has changed, and it has an embedded USB-to-serial [all …]
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/freebsd/sys/contrib/device-tree/Bindings/sound/ |
H A D | wm8994.txt | 8 - compatible : One of "wlf,wm1811", "wlf,wm8994" or "wlf,wm8958". 10 - reg : the I2C address of the device for I2C, the chip select 13 - gpio-controller : Indicates this device is a GPIO controller. 14 - #gpio-cells : Must be 2. The first cell is the pin number and the 17 - power supplies for the device, as covered in 20 - for wlf,wm1811 and wlf,wm8958: 21 AVDD1-supply, AVDD2-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply, 22 DCVDD-supply, CPVDD-supply, SPKVDD1-supply, SPKVDD2-supply 23 - for wlf,wm8994: 24 AVDD1-supply, AVDD2-supply, DBVDD-supply, DCVDD-supply, CPVDD-supply, [all …]
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H A D | qcom,msm8916-wcd-analog.txt | 8 - compatible = "qcom,pm8916-wcd-analog-codec"; 9 - reg: represents the slave base address provided to the peripheral. 10 - interrupts: List of interrupts in given SPMI peripheral. 11 - interrupt-names: Names specified to above list of interrupts in same 12 order. List of supported interrupt names are: 13 "cdc_spk_cnp_int" - Speaker click and pop interrupt. 14 "cdc_spk_clip_int" - Speaker clip interrupt. 15 "cdc_spk_ocp_int" - Speaker over current protect interrupt. 16 "mbhc_ins_rem_det1" - jack insert removal detect interrupt 1. 17 "mbhc_but_rel_det" - button release interrupt. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
H A D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ARM Generic Interrupt Controller, version 3 10 - Marc Zyngier <maz@kernel.org> 15 Software Generated Interrupts (SGI), and Locality-specific Peripheral 19 - $ref: /schemas/interrupt-controller.yaml# 24 - items: 25 - enum: [all …]
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H A D | brcm,bcm7038-l1-intc.txt | 1 Broadcom BCM7038-style Level 1 interrupt controller 3 This block is a first level interrupt controller that is typically connected 4 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip 9 - 64, 96, 128, or 160 incoming level IRQ lines 11 - Most onchip peripherals are wired directly to an L1 input 13 - A separate instance of the register set for each CPU, allowing individual 16 - Atomic mask/unmask operations 18 - No polarity/level/edge settings 20 - No FIFO or priority encoder logic; software is expected to read all 21 2-5 status words to determine which IRQs are pending [all …]
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H A D | brcm,bcm7038-l1-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom BCM7038-style Level 1 interrupt controller 10 This block is a first level interrupt controller that is typically connected 11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip 16 - 64, 96, 128, or 160 incoming level IRQ lines 18 - Most onchip peripherals are wired directly to an L1 input 20 - A separate instance of the register set for each CPU, allowing individual [all …]
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H A D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC) 2 --------------------------------------------- 4 RISC-V cores include Control Status Registers (CSRs) which are local to each 5 CPU core (HART in RISC-V terminology) and can be read or written by software. 7 Every interrupt is ultimately routed through a hart's HLIC before it 10 The RISC-V supervisor ISA manual specifies three interrupt sources that are 11 attached to every HLIC: software interrupts, the timer interrupt, and external 13 timer interrupt comes from an architecturally mandated real-time timer that is 16 via the platform-level interrupt controller (PLIC). 18 All RISC-V systems that conform to the supervisor ISA specification are [all …]
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H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V Hart-Level Interrupt Controller (HLIC) 10 RISC-V cores include Control Status Registers (CSRs) which are local to 11 each CPU core (HART in RISC-V terminology) and can be read or written by 13 to the core. Every interrupt is ultimately routed through a hart's HLIC 16 The RISC-V supervisor ISA manual specifies three interrupt sources that are 17 attached to every HLIC namely software interrupts, the timer interrupt, and [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | qcom,ipa.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alex Elder <elder@kernel.org> 21 and has a distinct interrupt and a separately-defined address space. 28 - | 29 -------- --------- 31 | AP +<---. .----+ Modem | 32 | +--. | | .->+ | 34 -------- | | | | --------- [all …]
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H A D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec" 5 - reg : Address and length of the register set for the device 6 - interrupts : Should contain fec interrupt 7 - phy-mode : See ethernet.txt file in the same directory 10 - phy-supply : regulator that powers the Ethernet PHY. 11 - phy-handle : phandle to the PHY device connected to this device. 12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. 13 Use instead of phy-handle. 14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports 17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports [all …]
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H A D | fsl-tsec-phy.txt | 5 the definition of the PHY node in booting-without-of.txt for an example 9 - reg : Offset and length of the register set for the device, and optionally 14 - compatible : Should define the compatible device type for the 16 - "fsl,gianfar-tbi" 17 - "fsl,gianfar-mdio" 18 - "fsl,etsec2-tbi" 19 - "fsl,etsec2-mdio" 20 - "fsl,ucc-mdio" 21 - "fsl,fman-mdio" 23 - "gianfar" [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/nfc/ |
H A D | st,st-nci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/net/nfc/st,st-nci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 15 - st,st21nfcb-i2c 16 - st,st21nfcb-spi 17 - st,st21nfcc-i2c 19 reset-gpios: 22 ese-present: [all …]
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H A D | st-nci-spi.txt | 4 - compatible: Should be "st,st21nfcb-spi" 5 - spi-max-frequency: Maximum SPI frequency (<= 4000000). 6 - interrupts: GPIO interrupt to which the chip is connected 7 - reset-gpios: Output GPIO pin used to reset the ST21NFCB 10 - pinctrl-names: Contains only one value - "default". 11 - pintctrl-0: Specifies the pin control groups used for this controller. 12 - ese-present: Specifies that an ese is physically connected to the nfc 14 - uicc-present: Specifies that the uicc swp signal can be physically 17 Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4): 24 compatible = "st,st21nfcb-spi"; [all …]
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H A D | st-nci-i2c.txt | 4 - compatible: Should be "st,st21nfcb-i2c" or "st,st21nfcc-i2c". 5 - clock-frequency: I²C work frequency. 6 - reg: address on the bus 7 - interrupts: GPIO interrupt to which the chip is connected 8 - reset-gpios: Output GPIO pin used to reset the ST21NFCB 11 - pinctrl-names: Contains only one value - "default". 12 - pintctrl-0: Specifies the pin control groups used for this controller. 13 - ese-present: Specifies that an ese is physically connected to the nfc 15 - uicc-present: Specifies that the uicc swp signal can be physically 18 Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | pinctrl-mcp23s08.txt | 2 8-/16-bit I/O expander with serial interface (I2C/SPI) 5 - compatible : Should be 6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version 7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version 8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or 9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip 11 - "microchip,mcp23s08" for 8 GPIO SPI version 12 - "microchip,mcp23s17" for 16 GPIO SPI version 13 - "microchip,mcp23s18" for 16 GPIO SPI version 14 - "microchip,mcp23008" for 8 GPIO I2C version or [all …]
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/freebsd/sys/contrib/device-tree/Bindings/ata/ |
H A D | pata-arasan.txt | 4 - compatible: "arasan,cf-spear1340" 5 - reg: Address range of the CF registers 6 - interrupt: Should contain the CF interrupt number 7 - clock-frequency: Interface clock rate, in Hz, one of 21 - arasan,broken-udma: if present, UDMA mode is unusable 22 - arasan,broken-mwdma: if present, MWDMA mode is unusable 23 - arasan,broken-pio: if present, PIO mode is unusable 24 - dmas: one DMA channel, as described in bindings/dma/dma.txt 26 - dma-names: the corresponding channel name, must be "data" 31 compatible = "arasan,cf-spear1340"; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/iio/addac/ |
H A D | adi,ad74115.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...] |
/freebsd/sys/contrib/device-tree/Bindings/pci/ |
H A D | brcm,iproc-pcie.txt | 4 - compatible: 5 "brcm,iproc-pcie" for the first generation of PAXB based controller, 7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based 9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based 11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based 13 PAXB-based root complex is used for external endpoint devices. PAXC-based 15 - reg: base address and length of the PCIe controller I/O register space 16 - #interrupt-cells: set to <1> 17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the 18 mapping of the PCIe interface to interrupt numbers [all …]
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H A D | faraday,ftpci100.txt | 5 plain and dual PCI. The plain version embeds a cascading interrupt controller 7 chips interrupt controller. 14 - compatible: ranging from specific to generic, should be one of 15 "cortina,gemini-pci", "faraday,ftpci100" 16 "cortina,gemini-pci-dual", "faraday,ftpci100-dual" 18 "faraday,ftpci100-dual" 19 - reg: memory base and size for the host bridge 20 - #address-cells: set to <3> 21 - #size-cells: set to <2> 22 - #interrupt-cells: set to <1> [all …]
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/freebsd/sys/contrib/device-tree/Bindings/usb/ |
H A D | atmel-usb.txt | 6 - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers 8 - reg: Address and length of the register set for the device 9 - interrupts: Should contain ohci interrupt 10 - clocks: Should reference the peripheral, host and system clocks 11 - clock-names: Should contain three strings 15 - num-ports: Number of ports. 16 - atmel,vbus-gpio: If present, specifies a gpio that needs to be 18 - atmel,oc-gpio: If present, specifies a gpio that needs to be 22 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 25 clock-names = "ohci_clk", "hclk", "uhpck"; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/gpio/ |
H A D | gpio-thunderx.txt | 1 Cavium ThunderX/OCTEON-TX GPIO controller bindings 4 - reg: The controller bus address. 5 - gpio-controller: Marks the device node as a GPIO controller. 6 - #gpio-cells: Must be 2. 7 - First cell is the GPIO pin number relative to the controller. 8 - Second cell is a standard generic flag bitfield as described in gpio.txt. 11 - compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used. 12 - interrupt-controller: Marks the device node as an interrupt controller. 13 - #interrupt-cells: Must be present and have value of 2 if 14 "interrupt-controller" is present. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/ |
H A D | example-schema.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 # All the top-level keys are standard json-schema keywords except for 9 # file present at the URL. 10 $id: http://devicetree.org/schemas/example-schema.yaml# 11 # $schema is the meta-schema this schema should be validated with. 12 $schema: http://devicetree.org/meta-schemas/core.yaml# 17 - Rob Herring <robh@kernel.org> 20 A more detailed multi-line description of the binding. 44 - items: [all …]
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/freebsd/sys/contrib/device-tree/Bindings/media/ |
H A D | coda.txt | 1 Chips&Media Coda multi-standard codec IP 4 Coda codec IPs are present in i.MX SoCs in various versions, 8 - compatible : should be "fsl,<chip>-src" for i.MX SoCs: 9 (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27 10 (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51 11 (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53 12 (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q 13 - reg: should be register base and length as documented in the 15 - interrupts : Should contain the VPU interrupt. For CODA960, 16 a second interrupt is needed for the MJPEG unit. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/i2c/ |
H A D | i2c.txt | 8 ----------------------------- 10 - #address-cells - should be <1>. Read more about addresses below. 11 - #size-cells - should be <0>. 12 - compatible - name of I2C bus controller 21 ----------------------------- 26 - clock-frequency 29 - i2c-bus 31 devices and non-I2C devices, the 'i2c-bus' subnode can be used for 32 populating I2C devices. If the 'i2c-bus' subnode is present, only 34 '#address-cells' and '#size-cells' must be defined under this subnode [all …]
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