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/linux/drivers/soc/renesas/
H A Dr9a09g056-sys.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "rz-sysc.h"
35 #define SYS_RZV2N_FEATURE_SEC BIT(2)
70 dev_info(dev, "Detected Renesas %s %sn%d Rev %s%s%s%s%s\n", soc_dev_attr->family, in rzv2n_sys_print_id()
71 soc_dev_attr->soc_id, 41 + feature_flags, soc_dev_attr->revision, in rzv2n_sys_print_id()
73 feature_flags & SYS_RZV2N_FEATURE_G31 ? " GE3D (Mali-G31)" : "", in rzv2n_sys_print_id()
75 feature_flags & SYS_RZV2N_FEATURE_C55 ? " ISP (Mali-C55)" : ""); in rzv2n_sys_print_id()
77 /* Check CA55 PLL configuration */ in rzv2n_sys_print_id()
79 dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); in rzv2n_sys_print_id()
91 static bool rzv2n_regmap_readable_reg(struct device *dev, unsigned int reg) in rzv2n_regmap_readable_reg()
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g047.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
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H A Dr9a09g057.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
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