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/linux/drivers/soc/renesas/
H A Dr9a09g047-sys.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "rz-sysc.h"
17 #define SYS_LSI_MODE 0x300
19 * BOOTPLLCA[1:0]
20 * [0,0] => 1.1GHZ
21 * [0,1] => 1.5GHZ
22 * [1,0] => 1.6GHZ
26 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3
28 #define SYS_LSI_PRR 0x308
32 #define SYS_LSI_OTPTSU1TRMVAL0 0x330
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H A Dr9a09g057-sys.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "rz-sysc.h"
17 #define SYS_LSI_MODE 0x300
19 * BOOTPLLCA[1:0]
20 * [0,0] => 1.1GHZ
21 * [0,1] => 1.5GHZ
22 * [1,0] => 1.6GHZ
26 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3
28 #define SYS_LSI_PRR 0x308
29 #define SYS_LSI_PRR_GPU_DIS BIT(0)
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H A Dr9a09g056-sys.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "rz-sysc.h"
17 #define SYS_LSI_MODE 0x300
20 * BOOTPLLCA[1:0]
21 * [0,0] => 1.1GHZ
22 * [0,1] => 1.5GHZ
23 * [1,0] => 1.6GHZ
27 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3
29 #define SYS_LSI_PRR 0x308
30 #define SYS_LSI_PRR_GPU_DIS BIT(0)
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g047.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
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H A Dr9a09g057.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
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