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/linux/Documentation/devicetree/bindings/firmware/
H A Dnxp,imx95-scmi-pinctrl.yaml29 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
42 "input_reg" indicates the offset of select input register.
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx8ulp-pinctrl.yaml35 setting for one pin. The first 4 integers <mux_config_reg input_reg
46 "input_reg" indicates the offset of select input register.
H A Dfsl,imxrt1050.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
H A Dfsl,imxrt1170.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "input_reg" indicates the offset of select input register.
H A Dfsl,imx8m-pinctrl.yaml39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "input_reg" indicates the offset of select input register.
H A Dfsl,imx9-pinctrl.yaml40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "input_reg" indicates the offset of select input register.
H A Dfsl,imx7ulp-iomuxc1.yaml41 <mux_conf_reg input_reg mux_mode input_val> are specified
55 "input_reg" indicates the offset of select input register.
H A Dfsl,imx7d-pinctrl.yaml44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
57 "input_reg" indicates the offset of select input register.
H A Dfsl,imx35-pinctrl.yaml52 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
65 "input_reg" indicates the offset of select input register.
H A Dfsl,imx-pinctrl.txt26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx-scmi.c66 int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val; in pinctrl_scmi_imx_dt_node_to_map() local
112 input_reg = be32_to_cpu(*list++); in pinctrl_scmi_imx_dt_node_to_map()
128 if (!input_reg) { in pinctrl_scmi_imx_dt_node_to_map()
132 (input_reg - daisy_off) / 4); in pinctrl_scmi_imx_dt_node_to_map()
H A Dpinctrl-imx.h24 * @input_reg: the select input register offset for this pin if any
31 u16 input_reg; member
/linux/drivers/hid/intel-thc-hid/intel-quicki2c/
H A Dquicki2c-protocol.c204 u16 input_reg = le16_to_cpu(qcdev->dev_desc.input_reg); in quicki2c_reset() local
227 ret = thc_tic_pio_read(qcdev->thc_hw, input_reg, read_len, &prd_len, in quicki2c_reset()
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc-snvs.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6ull-pinfunc.h12 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx7ulp-pinfunc.h12 * <mux_conf_reg input_reg mux_mode input_val>
H A Dimx25-pinfunc.h13 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx51-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
/linux/drivers/input/touchscreen/
H A Diqs5xx.c901 bool input_reg = !iqs5xx->input; in fw_file_store() local
925 if (input_reg) { in fw_file_store()
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h12 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx93-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx8mn-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx8mm-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx95-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-pinfunc.h11 * <mux_reg input_reg mux_mode input_val>

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