Home
last modified time | relevance | path

Searched +full:input +full:- +full:ngpios (Results 1 – 25 of 49) sorted by relevance

12

/linux/Documentation/devicetree/bindings/gpio/
H A Dnuvoton,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim LIU <JJLIU0@nuvoton.com>
20 to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO.
22 - Support interrupt option for each input port and various interrupt
23 sensitivity options (level-high, level-low, edge-high, edge-low)
24 - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines.
25 nuvoton,input-ngpios GPIO lines is only for GPI.
26 nuvoton,output-ngpios GPIO lines is only for GPO.
[all …]
H A Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
19 - Support reset tolerance option for each output port
20 - Directly connected to APB bus and its shift clock is from APB bus clock
22 - Co-work with external signal-chained TTL components (74LV165/74LV595)
27 - aspeed,ast2400-sgpio
[all …]
H A Dpisosr-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/pisosr-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Parallel-in/Serial-out Shift Register GPIO Driver
10 This binding describes generic parallel-in/serial-out shift register
11 devices that can be used for GPI (General Purpose Input). This includes
12 SN74165 serial-out shift registers and the SN65HVS88x series of
16 - Frank Li <Frank.Li@nxp.com>
21 - pisosr-gpio
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
[all …]
H A Dintel,pinctrl-keembay.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
14 of pin directions, input/output values and configuration
19 const: intel,keembay-pinctrl
24 gpio-controller: true
26 '#gpio-cells':
29 ngpios:
[all …]
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
15 controller. It controls the input/output settings on the available pins and
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
[all …]
/linux/arch/arc/boot/dts/
H A Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
[all …]
H A Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <750000000>;
[all …]
/linux/drivers/regulator/
H A Dgpio-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * gpio-regulator.c
14 * Roger Quadros <ext-roger.quadros@nokia.com>
17 * non-controllable regulators, as well as for allowing testing on
28 #include <linux/regulator/gpio-regulator.h>
50 for (ptr = 0; ptr < data->nr_states; ptr++) in gpio_regulator_get_value()
51 if (data->states[ptr].gpios == data->state) in gpio_regulator_get_value()
52 return data->states[ptr].value; in gpio_regulator_get_value()
54 return -EINVAL; in gpio_regulator_get_value()
64 for (ptr = 0; ptr < data->nr_states; ptr++) in gpio_regulator_set_voltage()
[all …]
/linux/include/linux/regulator/
H A Dgpio-regulator.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * gpio-regulator.h
14 * Roger Quadros <ext-roger.quadros@nokia.com>
27 * struct gpio_regulator_state - state description
29 * @gpios: bitfield of gpio target-states for the value
32 * and the necessary gpio-state to achieve it.
34 * The n-th bit in the bitfield describes the state of the n-th GPIO
35 * from the gpios-array defined in gpio_regulator_config below.
43 * struct gpio_regulator_config - config structure
45 * @input_supply: Name of the input regulator supply
[all …]
/linux/drivers/gpio/
H A Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
50 * Note: The "value" register returns the input value when the GPIO is
51 * configured as an input.
111 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
113 return gpio->base + bank->rdata_reg; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
117 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
119 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
121 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
123 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
[all …]
H A Dgpio-em.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile GPIO Support - GIO
61 return ioread32(p->base0 + offs); in em_gio_read()
63 return ioread32(p->base1 + (offs - GIO_IDT0)); in em_gio_read()
70 iowrite32(value, p->base0 + offs); in em_gio_write()
72 iowrite32(value, p->base1 + (offs - GIO_IDT0)); in em_gio_write()
94 ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); in em_gio_irq_reqres()
96 dev_err(p->gpio_chip.parent, in em_gio_irq_reqres()
108 gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); in em_gio_irq_relres()
131 return -EINVAL; in em_gio_irq_set_type()
[all …]
H A Dgpio-npcm-sgpio.c1 // SPDX-License-Identifier: GPL-2.0
143 return gpio->base + bank->rdata_reg; in bank_reg()
145 return gpio->base + bank->wdata_reg; in bank_reg()
147 return gpio->base + bank->event_config; in bank_reg()
149 return gpio->base + bank->event_status; in bank_reg()
152 dev_WARN(gpio->chip.parent, "Getting here is an error condition"); in bank_reg()
175 *offset -= internal->nout_sgpio; in npcm_sgpio_irqd_to_data()
184 in_port = GPIO_BANK(gpio->nin_sgpio); in npcm_sgpio_init_port()
185 if (GPIO_BIT(gpio->nin_sgpio) > 0) in npcm_sgpio_init_port()
188 out_port = GPIO_BANK(gpio->nout_sgpio); in npcm_sgpio_init_port()
[all …]
H A Dgpio-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/gpio/uniphier-gpio.h>
44 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. in uniphier_gpio_bank_to_reg()
65 spin_lock_irqsave(&priv->lock, flags); in uniphier_gpio_reg_update()
66 tmp = readl(priv->regs + reg); in uniphier_gpio_reg_update()
69 writel(tmp, priv->regs + reg); in uniphier_gpio_reg_update()
70 spin_unlock_irqrestore(&priv->lock, flags); in uniphier_gpio_reg_update()
107 return !!(readl(priv->regs + reg_offset) & mask); in uniphier_gpio_offset_read()
154 for_each_set_clump8(i, bank_mask, mask, chip->ngpio) { in uniphier_gpio_set_multiple()
170 return -ENXIO; in uniphier_gpio_to_irq()
[all …]
H A Dgpio-macsmc.c1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
19 * Commands 0-6 are, presumably, the intended API.
60 * 0 = input
65 * 0 = input
85 return -1; in macsmc_gpio_nr()
97 struct apple_smc *smc = smcgp->smc; in macsmc_gpio_find_first_gpio_index()
107 return -ENODEV; in macsmc_gpio_find_first_gpio_index()
109 ret = apple_smc_get_key_by_index(smc, smc->key_count - 1, &last_key); in macsmc_gpio_find_first_gpio_index()
113 return -ENODEV; in macsmc_gpio_find_first_gpio_index()
117 count = smc->key_count; in macsmc_gpio_find_first_gpio_index()
[all …]
H A Dgpio-ts4900.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2016 Savoir-Faire Linux
18 * Some boards, such as TS-7970 do not have a separate input bit
37 regmap_read(priv->regmap, offset, &reg); in ts4900_gpio_get_direction()
54 return regmap_update_bits(priv->regmap, offset, TS4900_GPIO_OE, 0); in ts4900_gpio_direction_input()
65 * If changing from an input to an output, we need to first set the in ts4900_gpio_direction_output()
69 regmap_read(priv->regmap, offset, &reg); in ts4900_gpio_direction_output()
76 regmap_write(priv->regmap, offset, reg); in ts4900_gpio_direction_output()
80 ret = regmap_write(priv->regmap, offset, TS4900_GPIO_OE | in ts4900_gpio_direction_output()
83 ret = regmap_write(priv->regmap, offset, TS4900_GPIO_OE); in ts4900_gpio_direction_output()
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controller/arm-gic.h"
11 compatible = "amd,pensando-elba";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 dma-coherent;
19 compatible = "fixed-clock";
[all …]
/linux/drivers/of/unittest-data/
H A Doverlay_gpio_01.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <0>;
10 compatible = "unittest-gpio";
12 gpio-controller;
13 #gpio-cells = <2>;
14 ngpios = <2>;
15 gpio-line-names = "line-A", "line-B";
17 line-b {
[all …]
H A Doverlay_gpio_03.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <0>;
10 compatible = "unittest-gpio";
12 gpio-controller;
13 #gpio-cells = <2>;
14 ngpios = <2>;
15 gpio-line-names = "line-A", "line-B", "line-C", "line-D";
17 line-d {
[all …]
/linux/Documentation/admin-guide/gpio/
H A Dgpio-sim.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
6 The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
12 ------------------------
14 The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
21 **Group:** ``/config/gpio-sim``
23 This is the top directory of the gpio-sim configfs tree.
25 **Group:** ``/config/gpio-sim/gpio-device``
27 **Attribute:** ``/config/gpio-sim/gpio-device/dev_name``
29 **Attribute:** ``/config/gpio-sim/gpio-device/live``
32 attribute is read-only and allows the user-space to read the platform device
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-pcb8309.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x_pcb8309.dts - Device Tree file for PCB8309
5 /dts-v1/;
7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
10 model = "Microchip EVB - LAN9662";
11 compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
20 stdout-path = "serial0:115200n8";
23 gpio-restart {
24 compatible = "gpio-restart";
29 i2c-mux {
[all …]
/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.h1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
41 .mfpctl_reg = -1, \
42 .mfpctl_shift = -1, \
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <0>;
22 clock-names = "cpu_clk", "ddrclk", "powersave";
33 compatible = "marvell,kirkwood-mbus", "simple-bus";
[all …]
/linux/drivers/pinctrl/bcm/
H A Dpinctrl-iproc-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Broadcom
9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
30 #include <linux/pinctrl/pinconf-generic.h>
34 #include "../pinctrl-utils.h"
68 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
125 * Mapping from PINCONF pins to GPIO pins is 1-to-1
133 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
148 val = readl(chip->base + offset); in iproc_set_bit()
153 writel(val, chip->base + offset); in iproc_set_bit()
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-m100pfsevp.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
8 /dts-v1/;
11 #include "mpfs-m100pfs-fabric.dtsi"
30 stdout-path = "serial1:115200n8";
60 ngpios = <14>;
63 pmic-irq-hog {
64 gpio-hog;
[all …]

12