Home
last modified time | relevance | path

Searched +full:inline +full:- +full:crypto +full:- +full:engine (Results 1 – 25 of 50) sorted by relevance

12

/linux/drivers/soc/qcom/
H A Dice.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
96 #define qcom_ice_writel(engine, val, reg) \
97 writel((val), (engine)->bas
95 qcom_ice_writel(engine,val,reg) global() argument
98 qcom_ice_readl(engine,reg) global() argument
555 struct qcom_ice *engine; qcom_ice_create() local
719 struct qcom_ice *engine; qcom_ice_probe() local
[all...]
/linux/drivers/crypto/ccp/
H A Dccp-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Cryptographic Coprocessor (CCP) crypto API support
16 #include <crypto/algapi.h>
17 #include <crypto/aes.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/aead.h>
20 #include <crypto/ctr.h>
21 #include <crypto/hash.h>
22 #include <crypto/sha1.h>
23 #include <crypto/sha2.h>
[all …]
/linux/include/crypto/
H A Dpcrypt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * pcrypt - Parallel crypto engine.
13 #include <linux/crypto.h>
22 static inline void *pcrypt_request_ctx(struct pcrypt_request *req) in pcrypt_request_ctx()
24 return req->__ctx; in pcrypt_request_ctx()
27 static inline
30 return &req->padata; in pcrypt_request_padata()
33 static inline
/linux/drivers/mmc/host/
H A Dcqhci-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * CQHCI crypto engine (inline encryption) support
20 * Returns the crypto bits that should be set in bits 64-127 of the
23 static inline u64 cqhci_crypto_prep_task_desc(struct mmc_request *mrq) in cqhci_crypto_prep_task_desc()
25 if (!mrq->crypto_ctx) in cqhci_crypto_prep_task_desc()
28 /* We set max_dun_bytes_supported=4, so all DUNs should be 32-bit. */ in cqhci_crypto_prep_task_desc()
29 WARN_ON_ONCE(mrq->crypto_ctx->bc_dun[0] > U32_MAX); in cqhci_crypto_prep_task_desc()
32 CQHCI_CRYPTO_KEYSLOT(mrq->crypto_key_slot) | in cqhci_crypto_prep_task_desc()
33 mrq->crypto_ctx->bc_dun[0]; in cqhci_crypto_prep_task_desc()
38 static inline int cqhci_crypto_init(struct cqhci_host *host) in cqhci_crypto_init()
[all …]
H A Dcqhci-crypto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CQHCI crypto engine (inline encryption) support
8 #include <linux/blk-crypto.h>
9 #include <linux/blk-crypto-profile.h>
12 #include "cqhci-crypto.h"
14 /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
25 static inline struct cqhci_host *
28 return mmc_from_crypto_profile(profile)->cqe_private; in cqhci_host_from_crypto_profile()
35 u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg); in cqhci_crypto_program_key()
39 cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
[all …]
/linux/drivers/crypto/ccree/
H A Dcc_driver.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
5 * ARM CryptoCell Linux Crypto Driver
16 #include <linux/dma-mapping.h>
17 #include <crypto/algapi.h>
18 #include <crypto/internal/skcipher.h>
19 #include <crypto/aes.h>
20 #include <crypto/sha1.h>
21 #include <crypto/sha2.h>
22 #include <crypto/aead.h>
[all …]
H A Dcc_hw_queue_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
21 #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
75 DESC_DIRECTION_ILLEGAL = -1,
83 DMA_MODE_NULL = -1,
92 FLOW_MODE_NULL = -1,
180 #define CC_LAST_HW_KEY_SLOT (CC_FIRST_HW_KEY_SLOT + CC_NUM_HW_KEY_SLOTS - 1)
185 CC_NUM_CPP_KEY_SLOTS - 1)
208 * hw_desc_init() - Init a HW descriptor struct
211 static inline void hw_desc_init(struct cc_hw_desc *pdesc) in hw_desc_init()
[all …]
/linux/drivers/crypto/intel/keembay/
H A Docs-aes.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Keem Bay OCS AES Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
11 #include <linux/dma-mapping.h>
35 * struct ocs_aes_dev - AES device context.
43 * @engine: Crypto engine for the device.
52 struct crypto_engine *engine; member
56 * struct ocs_dll_desc - Descriptor of an OCS DMA Linked List.
81 * ocs_aes_bypass_op() - Use OCS DMA to copy data.
88 static inline int ocs_aes_bypass_op(struct ocs_aes_dev *aes_dev, in ocs_aes_bypass_op()
H A Docs-hcu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay OCS HCU Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
14 #include <crypto/sha2.h>
16 #include "ocs-hcu.h"
96 * struct ocs_hcu_dma_entry - An entry in an OCS DMA linked list.
100 * @ll_flags: Flags (Freeze @ terminate) for the DMA engine.
110 * struct ocs_hcu_dma_list - OCS-specific DMA linked list.
118 * The OCS DMA list is an array-backed list of OCS DMA descriptors. The array
129 static inline u32 ocs_hcu_num_chains(enum ocs_hcu_algo algo) in ocs_hcu_num_chains()
[all …]
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_common.h1 /* SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/crypto.h>
41 /* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
48 * Message request to config cpt lf for inline inbound ipsec.
49 * This message is only used between CPT PF <-> CPT VF
66 * Message request and response to get engine group number
82 * Message request and response to get kernel crypto limits
83 * This messages are only used between CPT PF <-> CPT VF
117 * engine type (SE, IE, AE).
131 static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot, in otx2_cpt_write64()
[all …]
/linux/drivers/mmc/core/
H A Dcrypto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MMC crypto engine (inline encryption) support
8 #include <linux/blk-crypto.h>
12 #include "crypto.h"
18 if (host->caps2 & MMC_CAP2_CRYPTO) in mmc_crypto_set_initial_state()
19 blk_crypto_reprogram_all_keys(&host->crypto_profile); in mmc_crypto_set_initial_state()
24 if (host->caps2 & MMC_CAP2_CRYPTO) in mmc_crypto_setup_queue()
25 blk_crypto_register(&host->crypto_profile, q); in mmc_crypto_setup_queue()
32 struct mmc_request *mrq = &mqrq->brq.mrq; in mmc_crypto_prepare_req()
35 if (!req->crypt_ctx) in mmc_crypto_prepare_req()
[all …]
H A Dcrypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * MMC crypto engine (inline encryption) support
25 static inline void mmc_crypto_set_initial_state(struct mmc_host *host) in mmc_crypto_set_initial_state()
29 static inline void mmc_crypto_setup_queue(struct request_queue *q, in mmc_crypto_setup_queue()
34 static inline void mmc_crypto_prepare_req(struct mmc_queue_req *mqrq) in mmc_crypto_prepare_req()
/linux/include/linux/
H A Dccp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #include <crypto/aes.h>
18 #include <crypto/sha1.h>
19 #include <crypto/sha2.h>
27 * ccp_present - check if a CCP device is present
29 * Returns zero if a CCP device is present, -ENODEV otherwise.
34 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
39 * ccp_version - get the version of the CCP
46 * ccp_enqueue_cmd - queue an operation for processing by the CCP
55 * result in a return code of -EBUSY.
[all …]
/linux/drivers/crypto/aspeed/
H A Daspeed-acry.c1 // SPDX-License-Identifier: GPL-2.0+
5 #include <crypto/engine.h>
6 #include <crypto/internal/akcipher.h>
7 #include <crypto/internal/rsa.h>
8 #include <crypto/scatterwalk.h>
11 #include <linux/dma-mapping.h>
25 dev_info((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
28 dev_dbg((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
36 #define ASPEED_ACRY_TRIGGER 0x000 /* ACRY Engine Control: trigger */
37 #define ASPEED_ACRY_DMA_CMD 0x048 /* ACRY Engine Control: Command */
[all …]
/linux/drivers/crypto/caam/
H A Dcaamhash.c1 // SPDX-License-Identifier: GPL-2.0+
3 * caam - Freescale FSL CAAM support for ahash functions of crypto API
6 * Copyright 2018-2019, 2023 NXP
8 * Based on caamalg.c crypto API driver.
13 * --------------- ---------------
14 * | JobDesc #1 |-------------------->| ShareDesc |
16 * --------------- | (operation) |
17 * ---------------
21 * --------------- ---------------
22 * | JobDesc #2 |-------------------->| ShareDesc |
[all …]
H A Dcaamalg.c1 // SPDX-License-Identifier: GPL-2.0+
3 * caam - Freescale FSL CAAM support for crypto API
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 * Copyright 2016-2019, 2023, 2025 NXP
8 * Based on talitos crypto API driver.
12 * --------------- ---------------
13 * | JobDesc #1 |-------------------->| ShareDesc |
15 * --------------- |------------->| (hashKey) |
17 * . | |-------->| (operation) |
18 * --------------- | | ---------------
[all …]
/linux/drivers/crypto/amcc/
H A Dcrypto4xx_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AMCC SoC PPC4xx Crypto Driver
8 * This file implements AMCC crypto offload Linux device driver for use with
17 #include <linux/crypto.h>
18 #include <linux/dma-mapping.h>
27 #include <asm/dcr-regs.h>
29 #include <crypto/aead.h>
30 #include <crypto/aes.h>
31 #include <crypto/ctr.h>
32 #include <crypto/gcm.h>
[all …]
/linux/arch/mips/include/asm/octeon/
H A Docteon-feature.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-mio-defs.h>
35 #include <asm/octeon/cvmx-rnm-defs.h>
40 /* CN68XX has different fields in word0 - word2 */
47 /* Does this Octeon support the ZIP offload engine? */
92 OCTEON_HAS_CRYPTO = 0x0001, /* Crypto acceleration using COP2 */
97 * octeon_has_crypto() - Check if this OCTEON has crypto acceleration support.
99 * Returns: Non-zero if the feature exists. Zero if the feature does not exist.
[all …]
/linux/drivers/crypto/
H A Dpadlock-sha.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Support for VIA PadLock hardware crypto engine.
11 #include <crypto/internal/hash.h>
12 #include <crypto/padlock.h>
13 #include <crypto/sha1.h>
14 #include <crypto/sha2.h>
20 #define PADLOCK_SHA_DESCSIZE (128 + ((PADLOCK_ALIGNMENT - 1) & \
21 ~(CRYPTO_MINALIGN - 1)))
27 static inline void *padlock_shash_desc_ctx(struct shash_desc *desc) in padlock_shash_desc_ctx()
55 struct crypto_shash *tfm = desc->tfm; in padlock_sha_update()
[all …]
H A Dgeode-aes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Copyright (C) 2004-2006, Advanced Micro Devices, Inc.
9 #include <linux/crypto.h>
11 #include <crypto/algapi.h>
12 #include <crypto/aes.h>
13 #include <crypto/internal/cipher.h>
14 #include <crypto/internal/skcipher.h>
19 #include "geode-aes.h"
27 static inline void
37 static inline void
[all …]
H A Dpadlock-aes.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Support for VIA PadLock hardware crypto engine.
11 #include <crypto/algapi.h>
12 #include <crypto/aes.h>
13 #include <crypto/internal/skcipher.h>
14 #include <crypto/padlock.h>
76 static inline int
87 static inline struct aes_ctx *aes_ctx_common(void *ctx) in aes_ctx_common()
97 static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm) in aes_ctx()
102 static inline struct aes_ctx *skcipher_aes_ctx(struct crypto_skcipher *tfm) in skcipher_aes_ctx()
[all …]
/linux/drivers/crypto/tegra/
H A Dtegra-se-aes.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
4 * Crypto driver to handle block cipher algorithms using NVIDIA Security Engine.
9 #include <linux/dma-mapping.h>
14 #include <crypto/aead.h>
15 #include <crypto/aes.h>
16 #include <crypto/engine.h>
17 #include <crypto/gcm.h>
18 #include <crypto/scatterwalk.h>
19 #include <crypto/xts.h>
[all …]
/linux/drivers/dma/idxd/
H A Didxd.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/percpu-rwsem.h>
16 #include <linux/crypto.h>
28 IDXD_DEV_NONE = -1,
48 IDXD_TYPE_UNKNOWN = -1,
85 #define INVALID_INT_HANDLE -1
262 IDXD_DEV_HALTED = -1,
359 int nr_rdbufs; /* non-reserved read buffers */
393 static inline unsigned int evl_ent_size(struct idxd_device *idxd) in evl_ent_size()
395 return idxd->hw.gen_cap.evl_support ? in evl_ent_size()
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dqcom,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
19 - qcom,msm8994-ufshc
20 - qcom,msm8996-ufshc
21 - qcom,qcs615-ufshc
22 - qcom,sdm845-ufshc
[all …]
/linux/include/linux/mmc/
H A Dhost.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #include <linux/fault-inject.h>
18 #include <linux/dma-direction.h>
19 #include <linux/blk-crypto-profile.h>
187 * ios->clock might be 0. For some controllers, setting 0Hz
197 * 1 for a read-only card
198 * -ENOSYS when not supported (equal to NULL callback)
207 * -ENOSYS when not supported (equal to NULL callback)
233 /* Optional callback to prepare for SD high-speed tuning */
236 /* Optional callback to execute SD high-speed tuning */
[all …]

12