Home
last modified time | relevance | path

Searched full:infracfg_ao (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/sound/
H A Dmediatek,mt7986-afe.yaml142 clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
143 <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
144 <&infracfg_ao CLK_INFRA_AUD_L_CK>,
145 <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
146 <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;
H A Dmt8186-afe-pcm.yaml123 clocks = <&infracfg_ao 44>, //CLK_INFRA_AO_AUDIO
124 <&infracfg_ao 54>, //CLK_INFRA_AO_AUDIO_26M_BCLK
H A Dmt8195-afe-pcm.yaml177 <&infracfg_ao 50>, //CLK_INFRA_AO_AUDIO_26M_B
H A Dmediatek,mt8188-afe.yaml187 mediatek,infracfg = <&infracfg_ao>;
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8195-sys-clock.yaml22 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
29 - mediatek,mt8195-infracfg_ao
58 infracfg_ao: syscon@10001000 {
59 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
H A Dmediatek,mt8186-sys-clock.yaml22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
32 - mediatek,mt8186-infracfg_ao
H A Dmediatek,mt8365-sys-clock.yaml15 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
H A Dmediatek,mt8188-sys-clock.yaml22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
H A Dmediatek,infracfg.yaml29 - mediatek,mt6779-infracfg_ao
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6779.dtsi156 infracfg_ao: clock-controller@10001000 { label
157 compatible = "mediatek,mt6779-infracfg_ao", "syscon";
197 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>;
205 clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
214 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>;
224 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;
234 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;
/linux/Documentation/devicetree/bindings/thermal/
H A Dmediatek,lvts-thermal.yaml120 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
121 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Ddevapc.yaml59 clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
/linux/Documentation/devicetree/bindings/ufs/
H A Dmediatek,ufs.yaml61 clocks = <&infracfg_ao CLK_INFRA_UFS>;
/linux/include/dt-bindings/clock/
H A Dmediatek,mt7988-clk.h139 /* INFRACFG_AO */
H A Dmt8183-clk.h183 /* INFRACFG_AO */
H A Dmt8186-clk.h157 /* INFRACFG_AO */
H A Dmediatek,mt8188-clk.h218 /* INFRACFG_AO */
H A Dmt8195-clk.h259 /* INFRACFG_AO */
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-infra_ao.c224 .compatible = "mediatek,mt8186-infracfg_ao",
H A Dclk-mt8195-infra_ao.c226 .compatible = "mediatek,mt8195-infracfg_ao",
H A Dclk-mt6779.c1301 { .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc },