| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | mediatek,infracfg.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
13 The Mediatek infracfg controller provides various clocks and reset outputs
23 - mediatek,mt2701-infracfg
24 - mediatek,mt2712-infracfg
25 - mediatek,mt6765-infracfg
26 - mediatek,mt6795-infracfg
28 - mediatek,mt6797-infracfg
29 - mediatek,mt7622-infracfg
30 - mediatek,mt7629-infracfg
31 - mediatek,mt7981-infracfg
[all …]
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| H A D | mediatek,mt8192-sys-clock.yaml | 21 - mediatek,mt8192-infracfg
50 infracfg: syscon@10001000 {
51 compatible = "mediatek,mt8192-infracfg", "syscon";
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| /freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/ |
| H A D | mediatek,infracfg.yaml | 4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
13 The Mediatek infracfg controller provides various clocks and reset outputs
23 - mediatek,mt2701-infracfg
24 - mediatek,mt2712-infracfg
25 - mediatek,mt6765-infracfg
26 - mediatek,mt6795-infracfg
28 - mediatek,mt6797-infracfg
29 - mediatek,mt7622-infracfg
30 - mediatek,mt7629-infracfg
31 - mediatek,mt7981-infracfg
[all...] |
| H A D | mediatek,infracfg.txt | 1 Mediatek infracfg controller
4 The Mediatek infracfg controller provides various clocks and reset
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6765-infracfg", "syscon"
14 - "mediatek,mt6797-infracfg", "syscon"
15 - "mediatek,mt7622-infracfg", "syscon"
16 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
17 - "mediatek,mt7629-infracfg", "syscon"
18 - "mediatek,mt7986-infracfg", "syscon"
[all …]
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| H A D | mediatek,mt8192-sys-clock.yaml | 21 - mediatek,mt8192-infracfg
50 infracfg: syscon@10001000 {
51 compatible = "mediatek,mt8192-infracfg", "syscon";
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| /freebsd/sys/contrib/device-tree/src/arm64/mediatek/ |
| H A D | mt7988a.dtsi | 83 infracfg: clock-controller@10001000 { label
84 compatible = "mediatek,mt7988-infracfg", "syscon";
111 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
112 <&infracfg CLK_INFRA_66M_PWM_HCK>,
113 <&infracfg CLK_INFRA_66M_PWM_CK1>,
114 <&infracfg CLK_INFRA_66M_PWM_CK2>,
115 <&infracfg CLK_INFRA_66M_PWM_CK3>,
116 <&infracfg CLK_INFRA_66M_PWM_CK4>,
117 <&infracfg CLK_INFRA_66M_PWM_CK5>,
118 <&infracfg CLK_INFRA_66M_PWM_CK6>,
[all …]
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| H A D | mt8365.dtsi | 287 infracfg: syscon@10001000 { label
288 compatible = "mediatek,mt8365-infracfg", "syscon";
326 mediatek,infracfg = <&infracfg>;
327 mediatek,infracfg-nao = <&infracfg_nao>;
343 mediatek,infracfg = <&infracfg>;
361 clocks = <&infracfg CLK_IFR_APU_AXI>,
373 mediatek,infracfg = <&infracfg>;
384 mediatek,infracfg = <&infracfg>;
392 mediatek,infracfg = <&infracfg>;
398 <&infracfg CLK_IFR_AUDIO>,
[all …]
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| H A D | mt7981b.dtsi | 60 infracfg: clock-controller@10001000 { label
61 compatible = "mediatek,mt7981-infracfg", "syscon";
88 clocks = <&infracfg CLK_INFRA_PWM_STA>,
89 <&infracfg CLK_INFRA_PWM_HCK>,
90 <&infracfg CLK_INFRA_PWM1_CK>,
91 <&infracfg CLK_INFRA_PWM2_CK>,
92 <&infracfg CLK_INFRA_PWM3_CK>;
102 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
103 <&infracfg CLK_INFRA_UART0_CK>;
113 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
[all …]
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| H A D | mt7986a.dtsi | 143 infracfg: infracfg@10001000 { label
144 compatible = "mediatek,mt7986-infracfg", "syscon";
203 <&infracfg CLK_INFRA_PWM_STA>,
204 <&infracfg CLK_INFRA_PWM1_CK>,
205 <&infracfg CLK_INFRA_PWM2_CK>;
228 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
241 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
252 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
253 <&infracfg CLK_INFRA_UART0_CK>;
256 <&infracfg CLK_INFRA_UART0_SEL>;
[all …]
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| H A D | mt8183.dtsi | 742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
809 infracfg: syscon@10001000 { label
810 compatible = "mediatek,mt8183-infracfg", "syscon";
[all …]
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| H A D | mt8167.dtsi | 26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
54 mediatek,infracfg = <&infracfg>;
80 mediatek,infracfg = <&infracfg>;
91 mediatek,infracfg = <&infracfg>;
99 mediatek,infracfg = <&infracfg>;
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| H A D | mt8192.dtsi | 459 infracfg: syscon@10001000 { label
460 compatible = "mediatek,mt8192-infracfg", "syscon";
512 <&infracfg CLK_INFRA_AUDIO_26M_B>,
513 <&infracfg CLK_INFRA_AUDIO>;
515 mediatek,infracfg = <&infracfg>;
521 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
523 mediatek,infracfg = <&infracfg>;
538 mediatek,infracfg = <&infracfg>;
579 mediatek,infracfg = <&infracfg>;
593 mediatek,infracfg = <&infracfg>;
[all …]
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| H A D | mt8173.dtsi | 159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
174 clocks = <&infracfg CLK_INFRA_CA53SEL>,
189 clocks = <&infracfg CLK_INFRA_CA72SEL>,
204 clocks = <&infracfg CLK_INFRA_CA72SEL>,
355 infracfg: power-controller@10001000 { label
356 compatible = "mediatek,mt8173-infracfg", "syscon";
481 mediatek,infracfg = <&infracfg>;
515 mediatek,infracfg = <&infracfg>;
533 clocks = <&infracfg CLK_INFRA_CLK_13M>,
542 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
[all …]
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| H A D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
213 infracfg: infracfg@10000000 { label
214 compatible = "mediatek,mt7622-infracfg",
225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
250 infracfg = <&infracfg>;
259 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
302 clocks = <&infracfg CLK_INFRA_TRNG>;
621 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
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| H A D | mt8188.dtsi | 911 compatible = "mediatek,mt8188-infracfg-ao", "syscon";
964 mediatek,infracfg = <&infracfg_ao>;
1025 mediatek,infracfg = <&infracfg_ao>;
1044 mediatek,infracfg = <&infracfg_ao>;
1060 mediatek,infracfg = <&infracfg_ao>;
1068 mediatek,infracfg = <&infracfg_ao>;
1076 mediatek,infracfg = <&infracfg_ao>;
1087 mediatek,infracfg = <&infracfg_ao>;
1102 mediatek,infracfg = <&infracfg_ao>;
1140 mediatek,infracfg = <&infracfg_ao>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | mt8192-afe-pcm.yaml | 30 mediatek,infracfg:
32 description: The phandle of the mediatek infracfg controller
63 - mediatek,infracfg
85 mediatek,infracfg = <&infracfg>;
91 <&infracfg CLK_INFRA_AUDIO>,
92 <&infracfg CLK_INFRA_AUDIO_26M_B>;
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| H A D | mt8186-afe-pcm.yaml | 32 mediatek,infracfg:
34 description: The phandle of the mediatek infracfg controller
102 - mediatek,infracfg
121 mediatek,infracfg = <&infracfg>;
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7615/ |
| H A D | soc.c | 23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init()
24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init()
25 dev_err(dev->mt76.dev, "Cannot find infracfg controller\n"); in mt7622_wmac_init()
26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
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| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | mediatek,iommu.yaml | 109 mediatek,infracfg:
111 description: The phandle to the mediatek infracfg syscon
198 - mediatek,infracfg
224 clocks = <&infracfg CLK_INFRA_M4U>;
226 mediatek,infracfg = <&infracfg>;
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| /freebsd/sys/contrib/device-tree/Bindings/power/ |
| H A D | mediatek,power-controller.yaml | 116 mediatek,infracfg:
118 description: phandle to the device containing the INFRACFG register range.
120 mediatek,infracfg-nao:
122 description: phandle to the device containing the INFRACFG-NAO register range.
180 mediatek,infracfg = <&infracfg>;
214 mediatek,infracfg = <&infracfg>;
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | mediatek-pcie-gen3.yaml | 270 clocks = <&infracfg 44>,
271 <&infracfg 40>,
272 <&infracfg 43>,
273 <&infracfg 97>,
274 <&infracfg 99>,
275 <&infracfg 111>;
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| /freebsd/sys/contrib/device-tree/Bindings/soc/mediatek/ |
| H A D | scpsys.txt | 32 - infracfg: must contain a phandle to the infracfg controller
65 infracfg = <&infracfg>;
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| /freebsd/sys/contrib/device-tree/Bindings/cpufreq/ |
| H A D | cpufreq-mediatek.txt | 70 clocks = <&infracfg CLK_INFRA_CPUSEL>,
192 clocks = <&infracfg CLK_INFRA_CA53SEL>,
204 clocks = <&infracfg CLK_INFRA_CA53SEL>,
216 clocks = <&infracfg CLK_INFRA_CA72SEL>,
228 clocks = <&infracfg CLK_INFRA_CA72SEL>,
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| /freebsd/sys/contrib/device-tree/Bindings/net/wireless/ |
| H A D | mediatek,mt76.txt | 20 - mediatek,infracfg: phandle to the infrastructure bus fabric syscon node
75 mediatek,infracfg = <&infracfg>;
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| /freebsd/sys/contrib/device-tree/src/arm/mediatek/ |
| H A D | mt7623.dtsi | 80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
276 infracfg = <&infracfg>;
304 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
306 clocks = <&infracfg CLK_INFRA_PMICSPI>,
[all …]
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