| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | memory.json | 5 … (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[1…
10 …ounts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and…
15 …0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and…
20 …0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and…
30 …0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and…
40 … (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[1…
45 …ounts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and…
50 …0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and…
55 …ounts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and…
60 …ounts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and…
[all …]
|
| H A D | marked.json | 15 … (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[1…
25 …0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and…
95 … (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[1…
110 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at…
120 …ounts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and…
145 …0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and…
160 … (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[1…
195 "BriefDescription": "Marked Branch Mispredicted. Includes direction and target."
200 …ounts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and…
205 "BriefDescription": "Marked TLBIE instruction finished. Includes TLBIE and TLBIEL instructions."
[all …]
|
| H A D | frontend.json | 5 …ounts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and…
10 …0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and…
15 …1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefet…
55 …0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and…
60 …0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and…
95 …0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and…
100 "BriefDescription": "A mispredicted branch completed. Includes direction and target."
105 …"BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand m…
|
| H A D | others.json | 25 …"BriefDescription": "Counts all instruction cache reloads includes demand, prefetch, prefetch turn…
45 … typically adds about 10 cycles to the latency of the instruction. This includes loads that cross …
50 … typically adds about 10 cycles to the latency of the instruction. This includes loads that cross …
55 …cally adds about 10 cycles to the latency of the instruction. This only includes stores that cross…
60 …cally adds about 10 cycles to the latency of the instruction. This only includes stores that cross…
|
| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_acpi.h | 71 * WORD - structure size in bytes (includes size field)
102 * WORD - structure size in bytes (includes size field)
108 * WORD - structure size in bytes (includes size field)
126 * WORD - structure size in bytes (includes size field)
162 * WORD - structure size in bytes (includes size field)
166 * WORD - structure size in bytes (includes size field)
185 * WORD - structure size in bytes (includes size field)
195 * WORD - structure size in bytes (includes size field)
210 * WORD - structure size in bytes (includes size field)
219 * WORD - structure size in bytes (includes size field)
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | floating-point.json | 6 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
13 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
20 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
27 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
34 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
41 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
48 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
55 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
62 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
69 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
|
| H A D | core.json | 11 …"PublicDescription": "The number of uOps retired. This includes all processor activity (instructio…
17 …"PublicDescription": "The number of branch instructions retired. This includes all types of archit…
23 …tructions retired, of any type, that were not correctly predicted. This includes those for which p…
29 …"PublicDescription": "The number of taken branches that were retired. This includes all types of a…
70 …e. Each increment represents one complete instruction. Since this event includes non-numeric instr…
77 …e. Each increment represents one complete instruction. Since this event includes non-numeric instr…
84 …e. Each increment represents one complete instruction. Since this event includes non-numeric instr…
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | frontend.json | 38 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
42 "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uop
[all...] |
| H A D | uncore-io.json | 113 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
123 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
133 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
143 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
153 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
163 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
173 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
203 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
213 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
223 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | frontend.json | 38 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
42 "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uop
[all...] |
| H A D | uncore-io.json | 113 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
123 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
133 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
143 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
153 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
163 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
173 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
203 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
213 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
223 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | frontend.json | 38 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
42 "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uop
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | uncore-io.json | 87 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
97 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
107 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
117 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
127 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
137 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
147 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
157 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
167 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
177 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | floating-point.json | 6 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
13 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
20 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
27 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
34 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
|
| H A D | core.json | 11 …"PublicDescription": "The number of micro-ops retired. This count includes all processor activity …
17 …"PublicDescription": "The number of branch instructions retired. This includes all types of archit…
23 …tructions retired, of any type, that were not correctly predicted. This includes those for which p…
29 …"PublicDescription": "The number of taken branches that were retired. This includes all types of a…
70 …e. Each increment represents one complete instruction. Since this event includes non-numeric instr…
77 …e. Each increment represents one complete instruction. Since this event includes non-numeric instr…
84 …e. Each increment represents one complete instruction. Since this event includes non-numeric instr…
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | floating-point.json | 6 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
13 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
20 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
27 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
34 …includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increme…
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | virtual-memory.json | 23 …lation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that p…
32 … Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that p…
41 …page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk interval…
66 …ation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that p…
75 …Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that p…
84 …page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk interval…
109 …lation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that p…
118 …ation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that p…
127 …Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that p…
136 …page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk interval…
|
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | virtual-memory.json | 23 …lation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that p…
32 … Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that p…
41 …page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk interval…
66 …ation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that p…
75 …Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that p…
84 …page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk interval…
109 …lation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that p…
118 …ation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that p…
127 …Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that p…
136 …page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk interval…
|
| /linux/drivers/thermal/ti-soc-thermal/ |
| H A D | Kconfig | 9 This includes alert interrupts generation and also the TSHUT
19 This includes trip points definitions, extrapolation rules and
48 This includes alert interrupts generation and also the TSHUT
60 This includes alert interrupts generation and also the TSHUT
72 This includes alert interrupts generation and also the TSHUT
|
| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | uncore-io.json | 113 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
123 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
133 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
143 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
153 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
163 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
193 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
203 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
213 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
223 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
[all …]
|
| /linux/arch/powerpc/include/uapi/asm/ |
| H A D | elf.h | 93 #define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
94 #define ELF_NFPREG 33 /* includes fpscr */
95 #define ELF_NVMX 34 /* includes all vector registers */
96 #define ELF_NVSX 32 /* includes all VSX registers */
98 #define ELF_NEBB 3 /* includes ebbrr, ebbhr, bescr */
99 #define ELF_NPMU 5 /* includes siar, sdar, sier, mmcr2, mmcr0 */
100 #define ELF_NPKEY 3 /* includes amr, iamr, uamor */
101 #define ELF_NDEXCR 2 /* includes dexcr, hdexcr */
102 #define ELF_NHASHKEYR 1 /* includes hashkeyr */
115 # define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
[all …]
|
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | realtek,usb2phy.yaml | 20 The USB architecture includes three XHCI controllers.
30 The USB architecture includes two XHCI controllers.
31 The controller#0 has one USB 2.0 PHY. The controller#1 includes two USB 2.0
38 The USB architecture includes three XHCI controllers.
46 The USB architecture includes three XHCI controllers.
54 The USB architecture includes three XHCI controllers.
|
| /linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | uncore-io.json | 107 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
117 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
127 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
137 …umber of cycles that the AD ring is being used at this ring stop. This includes when packets are …
147 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
157 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
167 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
177 …umber of cycles that the AK ring is being used at this ring stop. This includes when packets are …
187 …umber of cycles that the BL ring is being used at this ring stop. This includes when packets are …
197 …umber of cycles that the BL ring is being used at this ring stop. This includes when packets are …
[all …]
|
| /linux/drivers/ufs/host/ |
| H A D | Kconfig | 66 accessing the hardware which includes PHY configuration and vendor
81 accessing the hardware which includes PHY configuration and vendor
124 platform driver. UFS host on Samsung Exynos SoC includes HCI and
140 accessing the hardware which includes PHY configuration and vendor
152 accessing the hardware which includes PHY configuration and vendor
|
| /linux/drivers/rapidio/switches/ |
| H A D | Kconfig | 8 Includes support for IDT CPS-16/12/10/8 serial RapidIO switches.
14 Includes support for ITD CPS Gen.2 serial RapidIO switches.
20 Includes support for ITD RXS Gen.3 serial RapidIO switches.
|