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Searched +full:imx8qxp +full:- +full:hsio (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-hsio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
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/linux/Documentation/devicetree/bindings/clock/
H A Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
24 include/dt-bindings/clock/imx8-lpcg.h
29 - const: fsl,imx8qxp-lpcg
30 - items:
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qxp-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 phyx1_lpcg: clock-controller@5f090000 {
9 compatible = "fsl,imx8qxp-lpcg";
13 #clock-cells = <1>;
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
16 clock-output-names = "hsio_phyx1_pclk",
20 power-domains = <&pd IMX_SC_R_SERDES_1>;
24 compatible = "fsl,imx8qxp-hsio";
29 reg-names = "reg", "phy", "ctrl", "misc";
35 clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
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H A Dimx8dxl-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 phyx1_lpcg: clock-controller@5f090000 {
8 compatible = "fsl,imx8qxp-lpcg";
12 #clock-cells = <1>;
13 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
15 clock-output-names = "hsio_phyx1_pclk",
19 power-domains = <&pd IMX_SC_R_SERDES_1>;
23 compatible = "fsl,imx8qxp-hsio";
28 reg-names = "reg", "phy", "ctrl", "misc";
34 clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
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H A Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx95-clock.h"
14 #include "imx95-pinfunc.h"
15 #include "imx95-power.h"
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
29 /* i.MX8Q HSIO registers */
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
121 struct device *dev = priv->dev; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
127 if (lane->ctrl_index == 0) { /* PCIEA */ in imx_hsio_init()
128 lane->ctrl_off = 0; in imx_hsio_init()
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/linux/drivers/pmdomain/imx/
H A Dscu-pd.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
10 * single global power domain and implement the ->attach|detach_dev()
12 * From within the ->attach_dev(), we could get the OF node for
13 * the device that is being attached and then parse the power-domain
18 * Additionally, we need to implement the ->stop() and ->start()
20 * rather than using the above ->power_on|off() callbacks.
23 * 1. The ->attach_dev() of power domain infrastructure still does
32 * Update: Genpd assigns the ->of_node for the virtual device before it
33 * invokes ->attach_dev() callback, hence parsing for device resources via
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