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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dfsl,imx8qm-hsio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
9 hsio_axi_clk: clock-hsio-axi {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <400000000>;
13 clock-output-names = "hsio_axi_clk";
16 hsio_per_clk: clock-hsio-per {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
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H A Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
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H A Dimx8dxl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
14 #include <dt-bindings/thermal/thermal.h>
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H A Dimx8qxp-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 phyx1_lpcg: clock-controller@5f090000 {
9 compatible = "fsl,imx8qxp-lpcg";
13 #clock-cells = <1>;
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
16 clock-output-names = "hsio_phyx1_pclk",
20 power-domains = <&pd IMX_SC_R_SERDES_1>;
24 compatible = "fsl,imx8qxp-hsio";
29 reg-names = "reg", "phy", "ctrl", "misc";
35 clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
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H A Dimx8dxl-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 phyx1_lpcg: clock-controller@5f090000 {
8 compatible = "fsl,imx8qxp-lpcg";
12 #clock-cells = <1>;
13 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
15 clock-output-names = "hsio_phyx1_pclk",
19 power-domains = <&pd IMX_SC_R_SERDES_1>;
23 compatible = "fsl,imx8qxp-hsio";
28 reg-names = "reg", "phy", "ctrl", "misc";
34 clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
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H A Dimx8qm-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 compatible = "fsl,imx8q-pcie";
19 reg-names = "dbi", "config";
22 #interrupt-cells = <1>;
24 interrupt-names = "msi";
25 #address-cells = <3>;
26 #size-cells = <2>;
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H A Dimx8qm.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
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H A Dimx8qxp-mek.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include "imx8qxp.dtsi"
9 #include <dt-bindings/usb/pd.h>
13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
15 bt_sco_codec: audio-codec-bt {
16 compatible = "linux,bt-sco";
17 #sound-dai-cells = <1>;
21 stdout-path = &lpuart0;
24 imx8x_cm4: imx8x-cm4 {
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H A Dimx8dxl-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
24 stdout-path = &lpuart0;
27 imx8dxl-cm4 {
28 compatible = "fsl,imx8qxp-cm4";
30 mbox-names = "tx", "rx", "rxdb";
32 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
34 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
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H A Dimx8x-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 stdout-path = &lpuart3;
11 colibri_gpio_keys: gpio-keys {
12 compatible = "gpio-keys";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpiokeys>;
17 key-wakeup {
18 debounce-interval = <10>;
20 label = "Wake-Up";
22 wakeup-source;
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H A Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx95-clock.h"
14 #include "imx95-pinfunc.h"
15 #include "imx95-power.h"
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
24 include/dt-bindings/clock/imx8-lpcg.h
29 - const: fsl,imx8qxp-lpcg
30 - items:
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