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/linux/Documentation/devicetree/bindings/power/
H A Dfsl,imx-gpcv2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrey Smirnov <andrew.smirnov@gmail.com>
13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
16 Power domains contained within GPC node are generic power domain
18 Documentation/devicetree/bindings/power/power-domain.yaml, which are
21 IP cores belonging to a power domain should contain a 'power-domains'
27 - fsl,imx7d-gpc
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/linux/drivers/pmdomain/imx/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
3 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
4 obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o
5 obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8m-blk-ctrl.o
6 obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8mp-blk-ctrl.o
7 obj-$(CONFIG_SOC_IMX9) += imx93-pd.o
8 obj-$(CONFIG_IMX9_BLK_CTRL) += imx93-blk-ctrl.o
H A Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
53 * an if-statement should be used before setting and clearing this
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
89 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
93 ret = pm_runtime_get_sync(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
95 pm_runtime_put_noidle(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
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H A Dimx8mp-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
19 #include <dt-bindings/power/imx8mp-power.h>
104 regmap_update_bits(clk->regmap, GPR_REG2, in clk_hsio_pll_prepare()
110 /* de-assert PLL reset */ in clk_hsio_pll_prepare()
111 regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST); in clk_hsio_pll_prepare()
114 regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE); in clk_hsio_pll_prepare()
116 return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val, in clk_hsio_pll_prepare()
124 regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0); in clk_hsio_pll_unprepare()
131 return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK); in clk_hsio_pll_is_prepared()
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