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Searched +full:imx8 +full:- +full:mu +full:- +full:scu (Results 1 – 7 of 7) sorted by relevance

/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qm-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2020 NXP
8 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
9 gpio-ranges = <&iomuxc 0 0 6>,
15 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
16 gpio-ranges = <&iomuxc 0 40 4>,
23 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
24 gpio-ranges = <&iomuxc 0 80 4>,
30 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
31 gpio-ranges = <&iomuxc 0 114 2>,
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H A Dimx8qxp-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
8 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
9 gpio-ranges = <&iomuxc 1 56 12>,
17 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
18 gpio-ranges = <&iomuxc 0 89 9>,
24 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
25 gpio-ranges = <&iomuxc 0 123 1>,
31 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
32 gpio-ranges = <&iomuxc 0 146 4>,
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H A Dimx8dxl-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 compatible = "nxp,imx8dxl-fspi";
12 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
14 gpio-ranges = <&iomuxc 0 47 13>,
21 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
23 gpio-ranges = <&iomuxc 4 74 5>,
28 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
30 gpio-ranges = <&iomuxc 1 98 2>,
36 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
38 gpio-ranges = <&iomuxc 0 115 4>,
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dfsl,mu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Messaging Unit (MU)
10 - Dong Aisheng <aisheng.dong@nxp.com>
15 and control) through the MU interface. The MU also provides the ability
18 Because the MU manages the messaging between processors, the MU uses
20 Therefore, the MU must synchronize the accesses from one side to the
21 other. The MU accomplishes synchronization using two sets of matching
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/linux/Documentation/devicetree/bindings/firmware/
H A Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
18 in the LSIO subsystem. The current definition of this MU module provides
20 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
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/linux/drivers/firmware/imx/
H A Dimx-scu.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Implementation of the SCU IPC functions using MUs (client side).
36 /* SCU uses 4 Tx and 4 Rx channels */
43 /* temporarily store the SCU msg */
70 -EINVAL, /* IMX_SC_ERR_VERSION */
71 -EINVAL, /* IMX_SC_ERR_CONFIG */
72 -EINVAL, /* IMX_SC_ERR_PARM */
73 -EACCES, /* IMX_SC_ERR_NOACCESS */
74 -EACCES, /* IMX_SC_ERR_LOCKED */
75 -ERANGE, /* IMX_SC_ERR_UNAVAILABLE */
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/linux/drivers/mailbox/
H A Dimx-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
29 /* TX0/RX0/RXDB[0-3] */
127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
132 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
134 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
136 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
138 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
139 /* MU reset */
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