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Searched +full:imx6ul +full:- +full:tempmon (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dfsl,imx-anatop.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
16 - items:
17 - enum:
18 - fsl,imx6sl-anatop
19 - fsl,imx6sll-anatop
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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dimx-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/imx-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
15 - enum:
16 - fsl,imx6q-tempmon
17 - fsl,imx6sx-tempmon
18 - fsl,imx7d-tempmon
19 - items:
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
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H A Dimx6sll.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
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/freebsd/sys/arm/freescale/imx/
H A Dimx6_machdep.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
67 * interrupt controller, which is for use when the chip is in deep-sleep mode.
68 * We don't support deep sleep or have a GPC-PIC driver; we need all interrupts
74 * set the world right by just changing the interrupt-parent property of the soc
78 * 2020/11/25: The tempmon and pmu nodes are siblings (not children) of the soc
83 * - SOC node exists and has GPC as its interrupt parent.
84 * - GPC node exists and has GIC as its interrupt parent.
85 * - GIC node exists and is its own interrupt parent or has no parent.
89 * per-soc logic. We handle this at platform attach time rather than via the
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