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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
[all …]
H A Dimx6sll.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
[all …]
H A Dimx6ul-opos6uldev.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
5 /dts-v1/;
6 #include "imx6ul-opos6ul.dtsi"
7 #include "imx6ul-imx6ull-opos6uldev.dtsi"
11 compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul";
14 &iomuxc {
15 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>;
H A Dimx6ul-tqma6ul2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 #include "imx6ul.dtsi"
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulx-common.dtsi"
12 model = "TQ-Systems TQMa6UL2 SoM";
13 compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
17 fsl,tuning-step = <6>;
20 &iomuxc {
[all …]
H A Dimx6ul-tqma6ul2l.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 #include "imx6ul.dtsi"
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulxl-common.dtsi"
12 model = "TQ-Systems TQMa6UL2L SoM";
13 compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
17 fsl,tuning-step = <6>;
20 &iomuxc {
[all …]
H A Dimx6ul-tqma6ul1-mba6ulx.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 /dts-v1/;
9 #include "imx6ul-tqma6ul1.dtsi"
13 model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board";
14 compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>;
31 #address-cells = <1>;
[all …]
H A Dimx6ul-kontron-bl-43.dts1 // SPDX-License-Identifier: GPL-2.0
8 #include "imx6ul-kontron-bl.dts"
12 compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
13 "kontron,sl-imx6ul", "fsl,imx6ul";
16 compatible = "pwm-backlight";
18 brightness-levels = <0 4 8 16 32 64 128 255>;
19 default-brightness-level = <6>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_cap_touch>;
30 interrupt-parent = <&gpio5>;
[all …]
H A Dimx6ul-pico-pi.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
10 #include "imx6ul-pico.dtsi"
12 model = "TechNexion PICO-IMX6UL and PI baseboard";
13 compatible = "technexion,imx6ul-pic
[all...]
H A Dimx6ul-pico-hobbit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
10 #include "imx6ul-pico.dtsi"
12 model = "TechNexion PICO-IMX6UL and HOBBIT baseboard";
13 compatible = "technexion,imx6ul-pic
[all...]
H A Dimx6ul-litesom.dtsi4 * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
6 * This file is dual-licensed: you can use it either under the terms
44 #include "imx6ul.dtsi"
48 compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
56 &iomuxc {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_usdhc2>;
77 no-1-8-v;
78 non-removable;
79 keep-power-in-suspend;
[all …]
H A Dimx6ul-liteboard.dts4 * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
6 * This file is dual-licensed: you can use it either under the terms
44 /dts-v1/;
46 #include "imx6ul-litesom.dtsi"
50 compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom",
51 "fsl,imx6ul";
54 stdout-path = &uart1;
57 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
58 compatible = "regulator-fixed";
59 pinctrl-names = "default";
[all …]
H A Dimx6ull-tqma6ull2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulx-common.dtsi"
12 model = "TQ-Systems TQMa6ULL2 SoM";
13 compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
17 fsl,tuning-step = <6>;
19 max-frequency = <99000000>;
20 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
[all …]
H A Dimx6ull-tqma6ull2l.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulxl-common.dtsi"
13 compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
17 fsl,tuning-step = <6>;
19 max-frequency = <99000000>;
20 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
21 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
[all …]
H A Dimx6ull.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "imx6ul.dtsi"
6 #include "imx6ull-pinfunc.h"
7 #include "imx6ull-pinfunc-snvs.h"
9 /* Delete UART8 in AIPS-1 (i.MX6UL specific) */
10 /delete-node/ &uart8;
11 /* Delete CAAM node in AIPS-2 (i.MX6UL specific) */
12 /delete-node/ &crypto;
15 clock-frequency = <900000000>;
16 operating-points = <
[all …]
H A Dimx6ul-ccimx6ulsbcexpress.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "imx6ul.dtsi"
13 #include "imx6ul-ccimx6ulsom.dtsi"
18 "fsl,imx6ul";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_adc1>;
28 pinctrl-names = "default";
[all …]
H A Dimx6ull-phytec-segin-peb-eval-01.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
9 &iomuxc {
10 /delete-node/ gpio_keysgrp;
H A Dimx6ull-phytec-segin-peb-wlbt-05.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
9 &iomuxc {
10 /delete-node/ wlgrp;
H A Dimx6ull-phytec-segin-peb-av-02.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
7 #include "imx6ul-phytec-segin-peb-av-02.dtsi"
9 &iomuxc {
10 /delete-node/ edtft5406grp;
11 /delete-node/ stmpegrp;
H A Dimx6ull-phytec-phycore-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "imx6ul-phytec-phycore-som.dtsi"
10 model = "PHYTEC phyCORE-i.MX6 ULL";
11 compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull";
14 &iomuxc {
15 /delete-node/ gpioledssomgrp;
H A Dimx6ul-tx6ul-mainboard.dts2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
43 #include "imx6ul.dtsi"
44 #include "imx6ul-tx6ul.dtsi"
47 model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
48 compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
51 lcdif-24bit-pins-a = &pinctrl_disp0_3;
53 /delete-property/ mmc1;
57 /delete-node/ sound;
[all …]
H A Dimx6ull-phytec-segin.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "imx6ul-phytec-segin.dtsi"
10 model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
11 compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
14 &iomuxc {
15 /delete-node/ flexcan1engrp;
16 /delete-node/ rtcintgrp;
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx6ul-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale IMX6UL IOMUX Controller
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
17 - $ref: pinctrl.yaml#
22 - fsl,imx6ul-iomuxc
23 - fsl,imx6ull-iomuxc-snvs
[all …]
H A Dfsl,imx6ul-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
8 "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
9 - fsl,pins: each entry consists of 6 integers and represents the mux and config
12 imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
13 the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dfsl,imx-iomuxc-gpr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx-iomuxc-gpr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
13 i.MX Processors have an IOMUXC General Purpose Register group for
19 - items:
20 - enum:
21 - fsl,imx6q-iomuxc-gpr
22 - fsl,imx8mq-iomuxc-gpr
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_machdep.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
67 * interrupt controller, which is for use when the chip is in deep-sleep mode.
68 * We don't support deep sleep or have a GPC-PIC driver; we need all interrupts
74 * set the world right by just changing the interrupt-parent property of the soc
83 * - SOC node exists and has GPC as its interrupt parent.
84 * - GPC node exists and has GIC as its interrupt parent.
85 * - GIC node exists and is its own interrupt parent or has no parent.
89 * per-soc logic. We handle this at platform attach time rather than via the
93 * This just in: as of the import of dts files from linux 4.15 on 2018-02-10,
[all …]

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