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Searched +full:imx51 +full:- +full:esdhc (Results 1 – 9 of 9) sorted by relevance

/freebsd/sys/dts/arm/
H A Dimx51x.dtsi32 #address-cells = <1>;
33 #size-cells = <1>;
41 #address-cells = <1>;
42 #size-cells = <0>;
48 d-cache-line-size = <32>;
49 i-cache-line-size = <32>;
50 d-cache-size = <0x8000>;
51 i-cache-size = <0x8000>;
53 timebase-frequency = <0>;
54 bus-frequency = <0>;
[all …]
H A Defikamx.dts31 /dts-v1/;
36 compatible = "genesi,imx51-efikamx", "fsl,imx51";
52 esdhc@70004000 {
53 clock-frequency = <216000000>;
56 esdhc@70008000 {
57 clock-frequency = <216000000>;
71 clock-frequency = <3000000>; /* XXX */
121 bootargs = "-v";
H A Dimx53x.dtsi34 #address-cells = <1>;
35 #size-cells = <1>;
43 #address-cells = <1>;
44 #size-cells = <0>;
50 d-cache-line-size = <32>;
51 i-cache-line-size = <32>;
52 d-cache-size = <0x8000>;
53 i-cache-size = <0x8000>;
54 l2-cache-line-size = <32>;
55 l2-cache-line = <0x40000>;
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dfsl-imx-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
7 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
10 - compatible : Should be "fsl,<chip>-esdhc", the supported chips include
11 "fsl,imx25-esdhc"
12 "fsl,imx35-esdhc"
13 "fsl,imx51-esdhc"
14 "fsl,imx53-esdhc"
15 "fsl,imx6q-usdhc"
16 "fsl,imx6sl-usdhc"
17 "fsl,imx6sx-usdhc"
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H A Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx51.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx51-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
42 tzic: tz-interrupt-controller@e0000000 {
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H A Dimx50.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include "imx50-pinfunc.h"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/imx5-clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existin
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H A Dimx53.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx53-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controlle
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/freebsd/sys/dev/sdhci/
H A Dfsl_sdhci.c1 /*-
31 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs).
105 * Freescale-specific registers, or in some cases the layout of bits within the
106 * sdhci-defined register is different on Freescale. These names all begin with
112 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
161 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
177 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
178 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
179 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
180 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
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