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Searched +full:imx1 +full:- +full:pwm (Results 1 – 4 of 4) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx1.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx1-pinfunc.h"
7 #include <dt-bindings/clock/imx1-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
34 aitc: aitc-interrupt-controller@223000 {
35 compatible = "fsl,imx1-aitc", "fsl,avic";
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/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dimx-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX PWM controller
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 - $ref: pwm.yaml#
16 "#pwm-cells":
19 PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.
24 - enum:
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/freebsd/sys/dts/arm/
H A Dimx53x.dtsi34 #address-cells = <1>;
35 #size-cells = <1>;
43 #address-cells = <1>;
44 #size-cells = <0>;
50 d-cache-line-size = <32>;
51 i-cache-line-size = <32>;
52 d-cache-size = <0x8000>;
53 i-cache-size = <0x8000>;
54 l2-cache-line-size = <32>;
55 l2-cache-line = <0x40000>;
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H A Dimx51x.dtsi32 #address-cells = <1>;
33 #size-cells = <1>;
41 #address-cells = <1>;
42 #size-cells = <0>;
48 d-cache-line-size = <32>;
49 i-cache-line-size = <32>;
50 d-cache-size = <0x8000>;
51 i-cache-size = <0x8000>;
53 timebase-frequency = <0>;
54 bus-frequency = <0>;
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