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Searched +full:imx +full:- +full:irqsteer (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,irqsteer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale IRQSTEER Interrupt Multiplexer
10 - Lucas Stach <l.stach@pengutronix.de>
15 - const: fsl,imx-irqsteer
16 - items:
17 - enum:
18 - fsl,imx8m-irqsteer
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-img.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
13 img_pxl_clk: clock-img-pxl {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
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H A Dimx8qm-ss-lvds.dtsi1 // SPDX-License-Identifier: GPL-2.0+
9 clock-indices = <IMX_LPCG_CLK_4>;
15 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
21 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
35 interrupt-parent = <&irqsteer_lvds0>;
37 irqsteer_lvds0: interrupt-controller@56240000 {
38 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
41 interrupt-controller;
42 interrupt-parent = <&gic>;
43 #interrupt-cells = <1>;
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H A Dimx8-ss-lvds1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_lvds1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_lvds1: interrupt-controller@57240000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
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H A Dimx8-ss-mipi0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_mipi0>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_mipi0: interrupt-controller@56220000 {
15 compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
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H A Dimx8-ss-mipi1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_mipi1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_mipi1: interrupt-controller@57220000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hdmi-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HDMI blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
20 - const: fsl,imx8mp-hdmi-blk-ctrl
21 - const: syscon
26 '#power-domain-cells':
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/linux/drivers/irqchip/
H A Dirq-imx-irqsteer.c1 // SPDX-License-Identifier: GPL-2.0+
45 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index()
50 struct irqsteer_data *data = d->chip_data; in imx_irqsteer_irq_unmask()
51 int idx = imx_irqsteer_get_reg_index(data, d->hwirq); in imx_irqsteer_irq_unmask()
55 raw_spin_lock_irqsave(&data->lock, flags); in imx_irqsteer_irq_unmask()
56 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
57 val |= BIT(d->hwirq % 32); in imx_irqsteer_irq_unmask()
58 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
59 raw_spin_unlock_irqrestore(&data->lock, flags); in imx_irqsteer_irq_unmask()
64 struct irqsteer_data *data = d->chip_data; in imx_irqsteer_irq_mask()
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/linux/Documentation/devicetree/bindings/display/imx/
H A Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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