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Searched full:iatu (Results 1 – 19 of 19) sorted by relevance

/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml33 normal controller functioning. iATU memory IO region is also required
47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
68 iATU/eDMA registers common for all device functions. It's an
73 set of viewport CSRs mapped into the PL space. Note iATU is
92 Outbound iATU-capable memory-region which will be used to
H A Dsnps,dw-pcie.yaml42 are required for the normal controller work. iATU memory IO region is
56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
77 iATU/eDMA registers common for all device functions. It's an
82 set of viewport CSRs mapped into the PL space. Note iATU is
101 Outbound iATU-capable memory-region which will be used to access
H A Dsnps,dw-pcie-common.yaml27 iATU/eDMA registers. The particular sub-space is selected by the
233 auto-detected based on the iATU memory writability. So there is no
243 on the iATU memory writability. There is no point having a dedicated
260 configuration space registers, Port Logic registers, DMA and iATU
H A Dbaikal,bt1-pcie.yaml18 performed by software. There four in- and four outbound iATU regions
30 DBI, DBI2 and at least 4KB outbound iATU-capable region for the
H A Dst,stm32-pcie-ep.yaml27 - description: Internal Address Translation Unit (iATU) registers.
H A Dnvidia,tegra194-pcie-ep.yaml35 - description: iATU and DMA registers. This is where the iATU (internal
H A Dsophgo,sg2044-pcie.yaml28 - description: iATU registers
H A Dnvidia,tegra194-pcie.yaml34 - description: iATU and DMA registers. This is where the iATU (internal
H A Drockchip-dw-pcie-ep.yaml33 - description: Internal Address Translation Unit (iATU) registers
/linux/drivers/pci/controller/dwc/
H A Dpcie-designware.h66 /* Parameters for the waiting for iATU enabled routine */
148 * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each
149 * iATU region CSRs had been indirectly accessible by means of the dedicated
150 * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe
152 * iATU/eDMA CSRs space.
195 * introduced so eDMA and iATU could be accessed via a dedicated registers
232 * iATU Unroll-specific register definitions
531 * If iATU input addresses are offset from CPU physical addresses,
H A Dpcie-designware.c140 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ in dw_pcie_get_resources()
530 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in dw_pcie_prog_outbound_atu()
593 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
630 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_ep_inbound_atu()
840 dev_err(pci->dev, "No iATU regions found\n"); in dw_pcie_iatu_detect()
859 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", in dw_pcie_iatu_detect()
H A Dpcie-dw-rockchip.c345 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
347 * default.) If the host could write to BAR4, the iATU settings (for all other
H A Dpci-imx6.c1328 * In old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD in iATU Ctrl2
/linux/drivers/accel/habanalabs/common/pci/
H A Dpci.c206 * hl_pci_iatu_write() - iatu write routine.
241 * Configure the iATU inbound region.
304 * Configure the iATU outbound region 0.
404 /* Driver must sleep in order for FW to finish the iATU configuration */ in hl_pci_init()
/linux/include/linux/dma/
H A Dedma.h40 * iATU windows. That will be done by the controller
/linux/include/linux/habanalabs/
H A Dhl_boot_if.h283 * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled.
284 * This bit if set, means the iATU has been
/linux/include/linux/
H A Dpci-epf.h118 * @aligned_size: the size actually allocated to accommodate the iATU alignment
/linux/drivers/pci/endpoint/
H A Dpci-epf-core.c295 * Allocate enough memory to accommodate the iATU alignment in pci_epf_alloc_space()
/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c551 * goya_init_iatu - Initialize the iATU unit inside the PCI controller
555 * This is needed in case the firmware doesn't initialize the iATU
655 /* Check whether FW is configuring iATU */ in goya_early_init()
2744 * iATU to point to the start address of the MMU page tables in goya_hw_init()