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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dsnps,dw-pcie-ep.yaml33 normal controller functioning. iATU memory IO region is also required
47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
68 iATU/eDMA registers common for all device functions. It's an
73 set of viewport CSRs mapped into the PL space. Note iATU is
92 Outbound iATU-capable memory-region which will be used to
H A Dsnps,dw-pcie.yaml42 are required for the normal controller work. iATU memory IO region is
56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
77 iATU/eDMA registers common for all device functions. It's an
82 set of viewport CSRs mapped into the PL space. Note iATU is
101 Outbound iATU-capable memory-region which will be used to access
H A Dsnps,dw-pcie-common.yaml27 iATU/eDMA registers. The particular sub-space is selected by the
232 auto-detected based on the iATU memory writability. So there is no
242 on the iATU memory writability. There is no point having a dedicated
259 configuration space registers, Port Logic registers, DMA and iATU
H A Dbaikal,bt1-pcie.yaml18 performed by software. There four in- and four outbound iATU regions
30 DBI, DBI2 and at least 4KB outbound iATU-capable region for the
H A Dnvidia,tegra194-pcie-ep.yaml35 - description: iATU and DMA registers. This is where the iATU (internal
H A Dnvidia,tegra194-pcie.txt27 "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
H A Duniphier-pcie.txt19 "atu" - iATU registers for DWC version 4.80 or later
H A Dnvidia,tegra194-pcie.yaml34 - description: iATU and DMA registers. This is where the iATU (internal
H A Ddesignware-pcie.txt39 space registers, Port Logic registers, DMA and iATU (internal Address
H A Drockchip-dw-pcie-ep.yaml33 - description: Internal Address Translation Unit (iATU) registers
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie.c949 al_reg_write32(&regs->port_regs->iatu.index, reg); in al_pcie_ecrc_gen_ob_atu_enable()
950 reg = al_reg_read32(&regs->port_regs->iatu.cr2); in al_pcie_ecrc_gen_ob_atu_enable()
952 reg = al_reg_read32(&regs->port_regs->iatu.cr1); in al_pcie_ecrc_gen_ob_atu_enable()
959 al_reg_write32(&regs->port_regs->iatu.cr1, reg); in al_pcie_ecrc_gen_ob_atu_enable()
1815 * on EP mode only, turning on the iATU-enable bit (with the relevant mask in al_pcie_port_config()
2406 * From SNPS (also included in the data book) Dynamic iATU Programming in al_pcie_atu_region_set()
2409 * (core_clk), you must not update the iATU registers while operations in al_pcie_atu_region_set()
2410 * are in progress on the AHB/AXI bridge slave interface. The iATU in al_pcie_atu_region_set()
2417 * Do not allow configuring Outbound iATU after link is started in al_pcie_atu_region_set()
2422 al_err("PCIe %d: setting OB iATU after link is started is not allowed\n", in al_pcie_atu_region_set()
[all …]
H A Dal_hal_pcie_regs.h110 struct al_pcie_core_iatu_regs iatu; member
478 /**** iATU, Control Register 1 ****/
484 * Number Match Enable" bit of the "iATU Control 2 Register" is set
489 /**** iATU, Control Register 2 ****/
H A Dal_hal_pcie.h1091 * an access is a hit in iATU if the:
1180 * that matches the iATU
1217 * @param direction input: iATU direction (IB/OB)
1218 * @param index input: iATU index
1219 * @param enable output: AL_TRUE if the iATU is enabled
1220 * @param base_addr output: the iATU base address
1221 * @param target_addr output: the iATU target address
H A Dal_hal_pcie_axi_reg.h858 /* Enable outbound configuration access through iATU. */
/freebsd/sys/dev/pci/
H A Dpci_dw.c210 "Cannot detect number of output iATU regions; read %#x\n", in pci_dw_detect_out_atu_regions_legacy()
277 "Cannot map outbound region %d in unroll mode iATU\n", idx); in pci_dw_map_out_atu_unroll()
309 "Cannot map outbound region %d in legacy mode iATU\n", idx); in pci_dw_map_out_atu_legacy()
784 device_printf(dev, "Using iATU %s mode\n", in pci_dw_init()
794 "Cannot allocate iATU space (rid: %d)\n", in pci_dw_init()
806 device_printf(dev, "Cannot get iATU space memory\n"); in pci_dw_init()
817 device_printf(sc->dev, "Detected outbound iATU regions: %d\n", in pci_dw_init()
H A Dpci_dw.h64 /* Legacy (pre-4.80) iATU mode */
82 /* Modern (4.80+) "unroll" iATU mode */