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/linux/sound/soc/hisilicon/
H A Dhi6210-i2s.c3 * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
31 #include "hi6210-i2s.h"
80 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val) in hi6210_write_reg() argument
82 writel(val, i2s->base + reg); in hi6210_write_reg()
85 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg) in hi6210_read_reg() argument
87 return readl(i2s->base + reg); in hi6210_read_reg()
93 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev); in hi6210_i2s_startup() local
98 regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val); in hi6210_i2s_startup()
100 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4)); in hi6210_i2s_startup()
102 for (n = 0; n < i2s->clocks; n++) { in hi6210_i2s_startup()
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/linux/sound/soc/tegra/
H A Dtegra210_i2s.c5 // tegra210_i2s.c - Tegra210 I2S driver
33 * is required to select i2s4b for it to be functional for I2S
51 static void tegra210_i2s_set_slot_ctrl(struct tegra210_i2s *i2s, in tegra210_i2s_set_slot_ctrl() argument
56 regmap_write(i2s->regmap, TEGRA210_I2S_SLOT_CTRL + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_set_slot_ctrl()
58 regmap_write(i2s->regmap, TEGRA210_I2S_TX_SLOT_CTRL + i2s->soc_data->tx_offset, in tegra210_i2s_set_slot_ctrl()
60 regmap_write(i2s->regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask); in tegra210_i2s_set_slot_ctrl()
66 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_set_clock_rate() local
70 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val); in tegra210_i2s_set_clock_rate()
72 /* No need to set rates if I2S is being operated in slave */ in tegra210_i2s_set_clock_rate()
76 err = clk_set_rate(i2s->clk_i2s, clock_rate); in tegra210_i2s_set_clock_rate()
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/linux/sound/soc/jz4740/
H A Djz4740-i2s.c97 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); in jz4740_i2s_startup() local
105 if (!i2s->soc_info->shared_fifo_flush) { in jz4740_i2s_startup()
107 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); in jz4740_i2s_startup()
109 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); in jz4740_i2s_startup()
121 if (i2s->soc_info->shared_fifo_flush) in jz4740_i2s_startup()
122 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); in jz4740_i2s_startup()
124 ret = clk_prepare_enable(i2s->clk_i2s); in jz4740_i2s_startup()
128 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); in jz4740_i2s_startup()
135 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); in jz4740_i2s_shutdown() local
140 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); in jz4740_i2s_shutdown()
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/linux/sound/soc/adi/
H A Daxi-i2s.c60 struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai); in axi_i2s_trigger() local
83 regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); in axi_i2s_trigger()
91 struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai); in axi_i2s_hw_params() local
98 bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1; in axi_i2s_hw_params()
100 regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) | in axi_i2s_hw_params()
109 struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai); in axi_i2s_startup() local
118 regmap_write(i2s->regmap, AXI_I2S_REG_RESET, mask); in axi_i2s_startup()
122 &i2s->rate_constraints); in axi_i2s_startup()
126 return clk_prepare_enable(i2s->clk_ref); in axi_i2s_startup()
132 struct axi_i2s *i2s = snd_soc_dai_get_drvdata(dai); in axi_i2s_shutdown() local
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/linux/sound/soc/sunxi/
H A Dsun4i-i2s.c183 /* Register fields for i2s */
196 unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *i2s);
205 int (*set_chan_cfg)(const struct sun4i_i2s *i2s,
208 int (*set_fmt)(const struct sun4i_i2s *i2s, unsigned int fmt);
225 /* Register fields for i2s */
278 static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) in sun4i_i2s_get_bclk_parent_rate() argument
280 return i2s->mclk_freq; in sun4i_i2s_get_bclk_parent_rate()
283 static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s) in sun8i_i2s_get_bclk_parent_rate() argument
285 return clk_get_rate(i2s->mod_clk); in sun8i_i2s_get_bclk_parent_rate()
288 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, in sun4i_i2s_get_bclk_div() argument
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/linux/sound/soc/google/
H A Dchv3-i2s.c9 * The I2S interface consists of two ring buffers - one for RX and one for
70 .name = "chv3-i2s",
101 static inline void chv3_i2s_wr(struct chv3_i2s_dev *i2s, int offset, u32 val) in chv3_i2s_wr() argument
103 writel(val, i2s->iobase + offset); in chv3_i2s_wr()
106 static inline u32 chv3_i2s_rd(struct chv3_i2s_dev *i2s, int offset) in chv3_i2s_rd() argument
108 return readl(i2s->iobase + offset); in chv3_i2s_rd()
113 struct chv3_i2s_dev *i2s = data; in chv3_i2s_isr() local
116 reg = readl(i2s->iobase_irq + I2S_IRQ_CLR); in chv3_i2s_isr()
121 snd_pcm_period_elapsed(i2s->rx_substream); in chv3_i2s_isr()
124 snd_pcm_period_elapsed(i2s->tx_substream); in chv3_i2s_isr()
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/linux/sound/soc/loongson/
H A Dloongson_i2s.c3 // Common functions for loongson I2S controller driver
34 struct loongson_i2s *i2s = snd_soc_dai_get_drvdata(dai); in loongson_i2s_trigger() local
44 regmap_update_bits(i2s->regmap, LS_I2S_CTRL, mask, mask); in loongson_i2s_trigger()
51 regmap_update_bits(i2s->regmap, LS_I2S_CTRL, mask, 0); in loongson_i2s_trigger()
64 struct loongson_i2s *i2s = snd_soc_dai_get_drvdata(dai); in loongson_i2s_hw_params() local
65 u32 clk_rate = i2s->clk_rate; in loongson_i2s_hw_params()
66 u32 sysclk = i2s->sysclk; in loongson_i2s_hw_params()
74 switch (i2s->rev_id) { in loongson_i2s_hw_params()
85 regmap_write(i2s->regmap, LS_I2S_CFG, val); in loongson_i2s_hw_params()
95 regmap_read(i2s->regmap, LS_I2S_CFG, &val); in loongson_i2s_hw_params()
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H A Dloongson_i2s_pci.c3 // loongson_i2s_pci.c -- Loongson I2S controller driver
19 #define DRIVER_NAME "loongson-i2s-pci"
81 struct loongson_i2s *i2s; in loongson_i2s_pci_probe() local
89 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); in loongson_i2s_pci_probe()
90 if (!i2s) in loongson_i2s_pci_probe()
93 i2s->rev_id = pdev->revision; in loongson_i2s_pci_probe()
94 i2s->dev = dev; in loongson_i2s_pci_probe()
95 pci_set_drvdata(pdev, i2s); in loongson_i2s_pci_probe()
97 i2s->reg_base = pcim_iomap_region(pdev, 0, DRIVER_NAME); in loongson_i2s_pci_probe()
98 if (IS_ERR(i2s->reg_base)) { in loongson_i2s_pci_probe()
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H A Dloongson_i2s.h3 * ALSA I2S interface for the Loongson platform
15 /* I2S Common Registers */
16 #define LS_I2S_VER 0x00 /* I2S Version */
17 #define LS_I2S_CFG 0x04 /* I2S Config */
18 #define LS_I2S_CTRL 0x08 /* I2S Control */
19 #define LS_I2S_RX_DATA 0x0C /* I2S DMA RX Address */
20 #define LS_I2S_TX_DATA 0x10 /* I2S DMA TX Address */
22 /* 2K2000 I2S Specify Registers */
23 #define LS_I2S_CFG1 0x14 /* I2S Config1 */
25 /* 7A2000 I2S Specify Registers */
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/linux/Documentation/devicetree/bindings/sound/
H A Dallwinner,sun4i-a10-i2s.yaml4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
7 title: Allwinner A10 I2S Controller
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
21 - const: allwinner,sun8i-a83t-i2s
22 - const: allwinner,sun8i-h3-i2s
24 - const: allwinner,sun8i-r40-i2s
25 - const: allwinner,sun8i-h3-i2s
27 - const: allwinner,sun8i-v3-i2s
28 - const: allwinner,sun8i-h3-i2s
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H A Drockchip-i2s.yaml4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
7 title: Rockchip I2S controller
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
22 - const: rockchip,rk3066-i2s
25 - rockchip,px30-i2s
26 - rockchip,rk1808-i2s
27 - rockchip,rk3036-i2s
28 - rockchip,rk3128-i2s
29 - rockchip,rk3188-i2s
30 - rockchip,rk3228-i2s
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H A Dsamsung-i2s.yaml4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
7 title: Samsung SoC I2S controller
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
25 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
32 samsung,exynos7-i2s: with all the available features of Exynos5 I2S.
33 Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
41 tesla,fsd-i2s: for 8/16/24bit stereo channel I2S for playback and
44 frequencies supported by Exynos7 I2S and 7.1 channel TDM support
49 - samsung,s3c6410-i2s
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H A Dnvidia,tegra210-i2s.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
7 title: Tegra210 I2S Controller
10 The Inter-IC Sound (I2S) controller implements full-duplex,
12 interfaces. It can interface with I2S compatible devices.
13 I2S controller can operate both in master and slave mode.
24 pattern: "^i2s@[0-9a-f]*$"
29 - nvidia,tegra210-i2s
30 - nvidia,tegra264-i2s
33 - nvidia,tegra234-i2s
34 - nvidia,tegra194-i2s
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H A Drockchip,i2s-tdm.yaml4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
7 title: Rockchip I2S/TDM Controller
10 The Rockchip I2S/TDM Controller is a Time Division Multiplexed
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
27 - rockchip,rk3588-i2s-tdm
28 - rockchip,rv1126-i2s-tdm
112 rockchip,i2s-rx-route:
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H A Dingenic,aic.yaml7 title: Ingenic SoCs AC97 / I2S Controller (AIC)
22 - ingenic,jz4740-i2s
23 - ingenic,jz4760-i2s
24 - ingenic,jz4770-i2s
25 - ingenic,jz4780-i2s
26 - ingenic,x1000-i2s
28 - const: ingenic,jz4725b-i2s
29 - const: ingenic,jz4740-i2s
43 - description: I2S clock
48 - const: i2s
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H A Dimg,i2s-in.txt1 Imagination Technologies I2S Input Controller
5 - compatible : Compatible list, must contain "img,i2s-in"
19 "rx" Single DMA channel used by all active I2S channels
21 - img,i2s-channels : Number of I2S channels instantiated in the I2S in block
25 - interrupts : Contains the I2S in interrupts. Depending on
27 or an interrupt per I2S channel. For the case where there is
31 - resets: Contains a phandle to the I2S in reset signal
37 i2s_in: i2s-in@18100800 {
38 compatible = "img,i2s-in";
45 img,i2s-channels = <6>;
H A Dimg,i2s-out.txt1 Imagination Technologies I2S Output Controller
5 - compatible : Compatible list, must contain "img,i2s-out"
20 "tx" Single DMA channel used by all active I2S channels
22 - img,i2s-channels : Number of I2S channels instantiated in the I2S out block
24 - resets: Contains a phandle to the I2S out reset signal
30 - interrupts : Contains the I2S out interrupts. Depending on
32 or an interrupt per I2S channel. For the case where there is
38 i2s_out: i2s-out@18100a00 {
39 compatible = "img,i2s-out";
47 img,i2s-channels = <6>;
H A Drockchip-max98090.txt6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
20 rockchip,model = "ROCKCHIP-I2S";
21 rockchip,i2s-controller = <&i2s>;
29 rockchip,model = "ROCKCHIP-I2S";
30 rockchip,i2s-controller = <&i2s>;
37 rockchip,model = "ROCKCHIP-I2S";
38 rockchip,i2s-controller = <&i2s>;
H A Dnvidia,tegra30-i2s.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra30-i2s.yaml#
7 title: NVIDIA Tegra30 I2S controller
17 - nvidia,tegra124-i2s
18 - nvidia,tegra30-i2s
20 - const: nvidia,tegra114-i2s
21 - const: nvidia,tegra30-i2s
30 const: i2s
36 const: i2s
59 i2s@70080300 {
60 compatible = "nvidia,tegra30-i2s";
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H A Dhisilicon,hi6210-i2s.txt1 * Hisilicon 6210 i2s controller
6 - "hisilicon,hi6210-i2s"
7 - reg: physical base address of the i2s controller unit and length of
9 - interrupts: should contain the i2s interrupt.
14 - "i2s-base"
25 Example for the hi6210 i2s controller:
27 i2s0: i2s@f7118000{
28 compatible = "hisilicon,hi6210-i2s";
29 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
33 clock-names = "dacodec", "i2s-base";
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H A Dsnps,designware-i2s.yaml4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
7 title: DesignWare I2S controller
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
19 - snps,designware-i2s
29 The interrupt line number for the I2S controller. Add this
30 parameter if the I2S controller that you are using does not
83 - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
84 - description: I2S-rx enabled control mask
86 The phandle to System Register Controller syscon node and the I2S-rx(ADC)
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/linux/sound/soc/intel/avs/boards/
H A DKconfig16 tristate "da7219 I2S board"
21 This adds support for AVS with DA7219 I2S codec configuration.
34 tristate "es8336 I2S board"
39 This adds support for AVS with ES8336 I2S codec configuration.
52 tristate "I2S test board"
54 This adds support for I2S test-board which can be used to verify
55 transfer over I2S interface with SSP loopback scenarios.
58 tristate "max98927 I2S board"
63 This adds support for AVS with MAX98927 I2S codec configuration.
68 tristate "max98357A I2S board"
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/linux/sound/soc/qcom/qdsp6/
H A Dq6prm.h6 /* Clock ID for Primary I2S IBIT */
8 /* Clock ID for Primary I2S EBIT */
10 /* Clock ID for Secondary I2S IBIT */
12 /* Clock ID for Secondary I2S EBIT */
14 /* Clock ID for Tertiary I2S IBIT */
16 /* Clock ID for Tertiary I2S EBIT */
18 /* Clock ID for Quartnery I2S IBIT */
20 /* Clock ID for Quartnery I2S EBIT */
22 /* Clock ID for Speaker I2S IBIT */
24 /* Clock ID for Speaker I2S EBIT */
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H A Dq6afe.h24 /* Clock ID for Primary I2S IBIT */
26 /* Clock ID for Primary I2S EBIT */
28 /* Clock ID for Secondary I2S IBIT */
30 /* Clock ID for Secondary I2S EBIT */
32 /* Clock ID for Tertiary I2S IBIT */
34 /* Clock ID for Tertiary I2S EBIT */
36 /* Clock ID for Quartnery I2S IBIT */
38 /* Clock ID for Quartnery I2S EBIT */
40 /* Clock ID for Speaker I2S IBIT */
42 /* Clock ID for Speaker I2S EBIT */
[all …]
/linux/sound/soc/meson/
H A Dg12a-tohdmitx.c35 "I2S A", "I2S B", "I2S C",
81 SOC_DAPM_ENUM_EXT("I2S Source", g12a_tohdmitx_i2s_mux_enum,
138 SND_SOC_DAPM_MUX("I2S SRC", SND_SOC_NOPM, 0, 0,
140 SND_SOC_DAPM_SWITCH("I2S OUT EN", SND_SOC_NOPM, 0, 0,
193 TOHDMITX_IN("I2S IN A", TOHDMITX_I2S_IN_A,
195 TOHDMITX_IN("I2S IN B", TOHDMITX_I2S_IN_B,
197 TOHDMITX_IN("I2S IN C", TOHDMITX_I2S_IN_C,
199 TOHDMITX_OUT("I2S OUT", TOHDMITX_I2S_OUT,
217 { "I2S SRC", "I2S A", "I2S IN A Playback" },
218 { "I2S SRC", "I2S B", "I2S IN B Playback" },
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