Home
last modified time | relevance | path

Searched full:i2s (Results 1 – 25 of 659) sorted by relevance

12345678910>>...27

/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dallwinner,sun4i-a10-i2s.yaml4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
7 title: Allwinner A10 I2S Controller
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
21 - const: allwinner,sun8i-a83t-i2s
22 - const: allwinner,sun8i-h3-i2s
24 - const: allwinner,sun8i-r40-i2s
25 - const: allwinner,sun8i-h3-i2s
27 - const: allwinner,sun8i-v3-i2s
28 - const: allwinner,sun8i-h3-i2s
[all …]
H A Drockchip-i2s.yaml4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
7 title: Rockchip I2S controller
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
22 - const: rockchip,rk3066-i2s
25 - rockchip,px30-i2s
26 - rockchip,rk1808-i2s
27 - rockchip,rk3036-i2s
28 - rockchip,rk3128-i2s
29 - rockchip,rk3188-i2s
30 - rockchip,rk3228-i2s
[all …]
H A Dnvidia,tegra210-i2s.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
7 title: Tegra210 I2S Controller
10 The Inter-IC Sound (I2S) controller implements full-duplex,
12 interfaces. It can interface with I2S compatible devices.
13 I2S controller can operate both in master and slave mode.
24 pattern: "^i2s@[0-9a-f]*$"
28 - const: nvidia,tegra210-i2s
31 - nvidia,tegra234-i2s
32 - nvidia,tegra194-i2s
33 - nvidia,tegra186-i2s
[all …]
H A Dsamsung-i2s.yaml4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
7 title: Samsung SoC I2S controller
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
25 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
32 samsung,exynos7-i2s: with all the available features of Exynos5 I2S
[all...]
H A Drockchip,i2s-tdm.yaml4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
7 title: Rockchip I2S/TDM Controller
10 The Rockchip I2S/TDM Controller is a Time Division Multiplexed
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
27 - rockchip,rk3588-i2s-tdm
28 - rockchip,rv1126-i2s-tdm
112 rockchip,i2s-rx-route:
[all …]
H A Dingenic,aic.yaml7 title: Ingenic SoCs AC97 / I2S Controller (AIC)
22 - ingenic,jz4740-i2s
23 - ingenic,jz4760-i2s
24 - ingenic,jz4770-i2s
25 - ingenic,jz4780-i2s
26 - ingenic,x1000-i2s
28 - const: ingenic,jz4725b-i2s
29 - const: ingenic,jz4740-i2s
43 - description: I2S clock
48 - const: i2s
[all …]
H A Dimg,i2s-in.txt1 Imagination Technologies I2S Input Controller
5 - compatible : Compatible list, must contain "img,i2s-in"
19 "rx" Single DMA channel used by all active I2S channels
21 - img,i2s-channels : Number of I2S channels instantiated in the I2S in block
25 - interrupts : Contains the I2S in interrupts. Depending on
27 or an interrupt per I2S channel. For the case where there is
31 - resets: Contains a phandle to the I2S in reset signal
37 i2s_in: i2s-in@18100800 {
38 compatible = "img,i2s-in";
45 img,i2s-channels = <6>;
H A Dintel,keembay-i2s.yaml5 $id: http://devicetree.org/schemas/sound/intel,keembay-i2s.yaml#
8 title: Intel KeemBay I2S
15 Intel KeemBay I2S
23 - intel,keembay-i2s
25 - intel,keembay-hdmi-i2s
32 - description: I2S registers
33 - description: I2S gen configuration
37 - const: i2s-regs
79 i2s3: i2s@20140000 {
80 compatible = "intel,keembay-i2s";
[all …]
H A Dimg,i2s-out.txt1 Imagination Technologies I2S Output Controller
5 - compatible : Compatible list, must contain "img,i2s-out"
20 "tx" Single DMA channel used by all active I2S channels
22 - img,i2s-channels : Number of I2S channels instantiated in the I2S out block
24 - resets: Contains a phandle to the I2S out reset signal
30 - interrupts : Contains the I2S out interrupts. Depending on
32 or an interrupt per I2S channel. For the case where there is
38 i2s_out: i2s-out@18100a00 {
39 compatible = "img,i2s-out";
47 img,i2s-channels = <6>;
H A Drockchip-max98090.txt6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
20 rockchip,model = "ROCKCHIP-I2S";
21 rockchip,i2s-controller = <&i2s>;
29 rockchip,model = "ROCKCHIP-I2S";
30 rockchip,i2s-controller = <&i2s>;
37 rockchip,model = "ROCKCHIP-I2S";
38 rockchip,i2s-controller = <&i2s>;
H A Dhisilicon,hi6210-i2s.txt1 * Hisilicon 6210 i2s controller
6 - "hisilicon,hi6210-i2s"
7 - reg: physical base address of the i2s controller unit and length of
9 - interrupts: should contain the i2s interrupt.
14 - "i2s-base"
25 Example for the hi6210 i2s controller:
27 i2s0: i2s@f7118000{
28 compatible = "hisilicon,hi6210-i2s";
29 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
33 clock-names = "dacodec", "i2s-base";
[all …]
H A Dnvidia,tegra30-i2s.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra30-i2s.yaml#
7 title: NVIDIA Tegra30 I2S controller
17 - nvidia,tegra124-i2s
18 - nvidia,tegra30-i2s
20 - const: nvidia,tegra114-i2s
21 - const: nvidia,tegra30-i2s
30 const: i2s
36 const: i2s
59 i2s@70080300 {
60 compatible = "nvidia,tegra30-i2s";
[all …]
H A Dsnps,designware-i2s.yaml4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
7 title: DesignWare I2S controller
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
19 - snps,designware-i2s
29 The interrupt line number for the I2S controller. Add this
30 parameter if the I2S controller that you are using does not
83 - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
84 - description: I2S-rx enabled control mask
86 The phandle to System Register Controller syscon node and the I2S
[all...]
H A Dnvidia,tegra30-i2s.txt1 NVIDIA Tegra30 I2S controller
4 - compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124,
5 must contain "nvidia,tegra124-i2s". Otherwise, must contain
6 "nvidia,<chip>-i2s" plus at least one of the above, where <chip> is
8 - reg : Should contain I2S registers location and length
14 - i2s
20 i2s@70080300 {
21 compatible = "nvidia,tegra30-i2s";
26 reset-names = "i2s";
H A Dst,stm32-i2s.yaml4 $id: http://devicetree.org/schemas/sound/st,stm32-i2s.yaml#
7 title: STMicroelectronics STM32 SPI/I2S Controller
13 The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode.
14 Only some SPI instances support I2S.
22 - st,stm32h7-i2s
34 - description: I2S parent clock for sampling rates multiple of 8kHz.
35 - description: I2S parent clock for sampling rates multiple of 11.025kHz.
61 description: Configure the I2S device as MCLK clock provider.
89 compatible = "st,stm32h7-i2s";
H A Dnvidia,tegra20-i2s.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
7 title: NVIDIA Tegra20 I2S Controller
10 The I2S Controller streams synchronous serial audio data between system
11 memory and an external audio device. The controller supports the I2S Left
20 const: nvidia,tegra20-i2s
29 const: i2s
66 i2s@70002800 {
67 compatible = "nvidia,tegra20-i2s";
72 reset-names = "i2s";
H A Dzte,zx-i2s.txt1 ZTE ZX296702 I2S controller
5 "zte,zx296718-i2s", "zte,zx296702-i2s"
6 "zte,zx296702-i2s"
7 - reg : Must contain I2S core's registers location and length
9 - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
21 i2s0: i2s@b005000 {
23 compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
H A Dxlnx,i2s.txt1 Device-Tree bindings for Xilinx I2S PL block
3 The IP supports I2S based playback/capture audio
6 - compatible: "xlnx,i2s-transmitter-1.0" for playback and
7 "xlnx,i2s-receiver-1.0" for capture
9 Required property common to both I2S playback and capture:
12 - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4.
18 compatible = "xlnx,i2s-receiver-1.0";
24 compatible = "xlnx,i2s-transmitter-1.0";
H A Dcirrus,ep9301-i2s.yaml4 $id: http://devicetree.org/schemas/sound/cirrus,ep9301-i2s.yaml#
7 title: Cirrus EP93xx I2S Controller
10 The I2S controller is used to stream serial audio data between the external
11 I2S CODECs’, ADCs/DACs, and the ARM Core. The controller supports I2S, Left-
22 const: cirrus,ep9301-i2s
68 i2s: i2s@80820000 {
69 compatible = "cirrus,ep9301-i2s";
H A Dnvidia,tegra20-i2s.txt1 NVIDIA Tegra 20 I2S controller
4 - compatible : "nvidia,tegra20-i2s"
5 - reg : Should contain I2S registers location and length
6 - interrupts : Should contain I2S interrupt
10 - i2s
21 i2s@70002800 {
22 compatible = "nvidia,tegra20-i2s";
27 reset-names = "i2s";
H A Ddesignware-i2s.txt1 DesignWare I2S controller
4 - compatible : Must be "snps,designware-i2s"
5 - reg : Must contain the I2S core's registers location and length
16 - interrupts: The interrupt line number for the I2S controller. Add this
17 parameter if the I2S controller that you are using does not support DMA.
27 soc_i2s: i2s@7ff90000 {
28 compatible = "snps,designware-i2s";
H A Dgoogle,chv3-i2s.yaml4 $id: http://devicetree.org/schemas/sound/google,chv3-i2s.yaml#
7 title: Google Chameleon v3 I2S device
13 I2S device for the Google Chameleon v3. The device handles both RX
18 const: google,chv3-i2s
39 i2s@c0060300 {
40 compatible = "google,chv3-i2s";
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dsii902x.txt15 - #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
18 - sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3
19 Each integer indicates which i2s pin is connected to which
20 audio fifo. The first integer selects i2s audio pin for the
22 (HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s
23 pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
24 but there can be no gaps. E.g. an i2s pin must be mapped to
36 If HDMI audio is configured the sii902x device becomes an I2S
63 sil,i2s-data-lanes = < 0 1 2 >;
H A Dsil,sii9022.yaml41 <0> if only I2S or S/PDIF pin is wired,
44 If HDMI audio is configured, the sii902x device becomes an I2S and/or
55 sil,i2s-data-lanes:
63 Each integer indicates which I2S pin is connected to which audio FIFO.
64 The first integer selects the I2S audio pin for the first audio FIFO#0
66 on. There are 4 FIFOs and 4 I2S pins (SD0 - SD3). Any I2S pin can be
67 connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be
115 sil,i2s-data-lanes = < 0 1 2 >;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dstarfive,jh7110-syscrg.yaml24 - description: External I2S TX bit clock
25 - description: External I2S TX left/right channel clock
26 - description: External I2S RX bit clock
27 - description: External I2S RX left/right channel clock
38 - description: External I2S TX bit clock
39 - description: External I2S TX left/right channel clock
40 - description: External I2S RX bit clock
41 - description: External I2S RX left/right channel clock

12345678910>>...27