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/linux/Documentation/devicetree/bindings/sound/
H A Dmicrochip,sama7g5-i2smcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip I2S Multi-Channel Controller
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
13 The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and
15 multi-channel audio codecs. It consists of a receiver, a transmitter and a
17 Client or Controller modes with receiver and/or transmitter active.
18 On later I2SMCC versions (starting with Microchip's SAMA7G5) I2S
[all …]
/linux/sound/soc/atmel/
H A Datmel-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Atmel I2S controller
29 * ---- I2S Controller Register map ----
39 #define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */
44 * ---- Control Register (Write-only) ----
46 #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */
47 #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */
55 * ---- Mode Register (Read/Write) ----
59 #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0)
63 #define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2)
[all …]
H A Dmchp-i2s-mcc.c1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for Microchip I2S Multi-channel controller
29 * ---- I2S Controller Register map ----
45 #define MCHP_I2SMCC_RHR 0x0030 /* Receiver Holding Register */
48 #define MCHP_I2SMCC_RHL0R 0x0040 /* Receiver Holding Left 0 Register */
49 #define MCHP_I2SMCC_RHR0R 0x0044 /* Receiver Holding Right 0 Register */
51 #define MCHP_I2SMCC_RHL1R 0x0048 /* Receiver Holding Left 1 Register */
52 #define MCHP_I2SMCC_RHR1R 0x004C /* Receiver Holding Right 1 Register */
54 #define MCHP_I2SMCC_RHL2R 0x0050 /* Receiver Holding Left 2 Register */
55 #define MCHP_I2SMCC_RHR2R 0x0054 /* Receiver Holding Right 2 Register */
[all …]
/linux/sound/soc/xilinx/
H A Dxlnx_i2s.c1 // SPDX-License-Identifier: GPL-2.0
3 // Xilinx ASoC I2S audio support
44 return -EINVAL; in xlnx_i2s_set_sclkout_div()
46 drv_data->sysclk = 0; in xlnx_i2s_set_sclkout_div()
48 writel(div, drv_data->base + I2S_I2STIM_OFFSET); in xlnx_i2s_set_sclkout_div()
58 drv_data->sysclk = freq; in xlnx_i2s_set_sysclk()
62 if (drv_data->is_32bit_lrclk) in xlnx_i2s_set_sysclk()
65 bits_per_sample = drv_data->data_width; in xlnx_i2s_set_sysclk()
67 drv_data->ratnum.num = freq / (bits_per_sample * drv_data->channels) / 2; in xlnx_i2s_set_sysclk()
68 drv_data->ratnum.den_step = 1; in xlnx_i2s_set_sysclk()
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Drda,rda5807.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Unisoc Communications RDA5807 FM radio receiver
10 - Paul Cercueil <paul@crapouillou.net>
15 - rda,rda5807
19 maxItems: 1
21 power-supply: true
31 rda,analog-out:
35 rda,i2s-out:
[all …]
/linux/sound/soc/fsl/
H A Dmpc5200_psc_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Freescale MPC5200 PSC in I2S mode
21 * PSC_I2S_RATES: sample rates supported by the I2S
23 * This driver currently only supports the PSC running in I2S slave mode,
31 * PSC_I2S_FORMATS: audio formats supported by the PSC I2S mode
44 dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i" in psc_i2s_hw_params()
64 dev_dbg(psc_dma->dev, "invalid format\n"); in psc_i2s_hw_params()
65 return -EINVAL; in psc_i2s_hw_params()
67 out_be32(&psc_dma->psc_regs->sicr, psc_dma->sicr | mode); in psc_i2s_hw_params()
90 dev_dbg(psc_dma->dev, "psc_i2s_set_sysclk(cpu_dai=%p, dir=%i)\n", in psc_i2s_set_sysclk()
[all …]
/linux/sound/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 tristate "SoC Audio for the Tegra System-on-Chip"
33 tristate "Tegra20 I2S interface"
37 Tegra20 I2S interface. You will also need to select the individual
55 tristate "Tegra30 I2S interface"
59 Tegra30 I2S interface. You will also need to select the individual
78 PDM receiver.
82 tristate "Tegra210 I2S module"
85 Config to enable the Inter-IC Sound (I2S) Controller which
86 implements full-duplex and bidirectional and single direction
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-gw54xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
8 #include "imx6qdl-gw54xx.dtsi"
9 #include <dt-bindings/media/tda1997x.h>
13 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
15 sound-digital {
16 compatible = "simple-audio-card";
17 simple-audio-card,name = "tda1997x-audio";
18 simple-audio-card,format = "i2s";
19 simple-audio-card,bitclock-master = <&sound_codec>;
[all …]
/linux/include/sound/
H A Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 /* receiver status 0 */
28 /* receiver status 1 */
30 /* receiver status 2 */
34 /* RX channel status byte 1 */
44 /* burst preamble Pc byte 1 */
48 /* burst preamble Pd byte 1 */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
[all …]
H A Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 #define AK4114_REG_RCS0 0x06 /* receiver status 0 */
18 #define AK4114_REG_RCS1 0x07 /* receiver status 1 */
20 #define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */
25 #define AK4114_REG_TXCSB1 0x0e /* TX channel status byte 1 */
30 #define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */
32 #define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
[all …]
H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #define AK4117_REG_RCS0 0x05 /* receiver status 0 */
16 #define AK4117_REG_RCS1 0x06 /* receiver status 1 */
17 #define AK4117_REG_RCS2 0x07 /* receiver status 2 */
19 #define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */
24 #define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */
26 #define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-roc-pc-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
6 /dts-v1/;
7 #include "rk3399-roc-pc.dtsi"
11 * 1. rk3399-roc-pc-plus is powered by dc_12v directly.
12 * 2. rk3399-roc-pc-plus has only vcc_bus_typec0 in schematic, which is coresponding
13 * to vcc_vbus_typec1 in rk3399-roc-pc.
15 * 3. vcc5v0_host is actually 2 regulators (host0, 1) controlled by the same gpio.
18 /delete-node/ &fusb1;
19 /delete-node/ &hub_rst;
[all …]
H A Drk3568-odroid-m1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,vop2.h>
15 model = "Hardkernel ODROID-M1";
16 compatible = "hardkernel,odroid-m1", "rockchip,rk3568";
29 stdout-path = "serial2:1500000n8";
32 dc_12v: regulator-dc-12v {
[all …]
H A Drk3568-rock-3b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/soc/rockchip,vop2.h>
13 compatible = "radxa,rock-3b", "rockchip,rk3568";
24 stdout-path = "serial2:1500000n8";
27 hdmi-con {
28 compatible = "hdmi-connector";
[all …]
H A Drk3588-friendlyelec-cm3588-nas.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/soc/rockchip,vop2.h>
15 #include <dt-bindings/usb/pd.h>
16 #include "rk3588-friendlyelec-cm3588.dtsi"
20 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
22 adc_key_recovery: adc-key-recovery {
[all …]
/linux/include/linux/mfd/
H A Dwl1273-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/linux/mfd/wl1273-core.h
5 * Some definitions for the wl1273 radio receiver/transmitter chip.
17 #define WL1273_FM_DRIVER_NAME "wl1273-fm"
21 #define WL1273_RSSI_LVL_GET 1
119 #define WL1273_RDS_ON 1
123 #define WL1273_AUDIO_ANALOG 1
126 #define WL1273_MODE_TX BIT(1)
131 #define WL1273_CODEC_CHILD BIT(1)
133 #define WL1273_RX_MONO 1
[all …]
/linux/sound/pci/ice1712/
H A Dpsc724.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
34 * VT1722 (Envy24GT) - 6 outputs, 4 inputs (only 2 used), 24-bit/96kHz
39 * one stereo ADC, no S/PDIF receiver
42 * AC-Link configuration ICE_EEP2_ACLINK=0x80
43 * use I2S, not AC97
45 * I2S converters feature ICE_EEP2_I2S=0x30
46 * I2S codec has no volume/mute control feature (bug!)
47 * I2S codec does not support 96KHz or 192KHz (bug!)
48 * I2S codec 24bits
[all …]
H A Dse.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Lowlevel functions for ONKYO WAVIO SE-90PCI and SE-200PCI
7 * Copyright (c) 2007 Shin-ya Okada sh_okada(at)d4.dion.ne.jp
8 * (at) -> @
29 /* ONKYO WAVIO SE-200PCI */
35 * one stereo ADC and a S/PDIF receiver connected
38 * AC-Link configuration ICE_EEP2_ACLINK=0x80
41 * I2S converters feature ICE_EEP2_I2S=0x78
42 * I2S codec has no volume/mute control feature
43 * I2S codec supports 96KHz and 192KHz
[all …]
H A Djuli.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 unsigned int analog:1;
31 #define AK4114_ADDR 0x20 /* S/PDIF receiver */
36 * supplied by external clock provided by Xilinx array and MK73-1 PLL frequency
42 * ice1724+ak4114-based cards, detects spdif input rate correctly.
46 * Juli uses the remaining three stereo-channels of its DAC to optionally
48 * I2S signals are routed by Xilinx, controlled by GPIOs.
65 #define GPIO_FREQ_44KHZ (1<<0)
69 #define GPIO_MULTI_2X (1<<2)
72 #define GPIO_INTERNAL_CLOCK (1<<4) /* 0 = external, 1 = internal */
[all …]
H A Dphase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Audio controller: VIA Envy24HT-S (slightly trimmed down Envy24HT, 4in/4out)
13 * Digital receiver: CS8414-CS (supported in this release)
18 * - CS directly from GPIO 10
19 * - CCL
[all...]
/linux/sound/pci/ctxfi/
H A Dcthw20k1.c1 // SPDX-License-Identifier: GPL-2.0-only
76 * Fixed-point value in 8.24 format for parameter channel */
82 u16 ctl:1;
83 u16 ccr:1;
84 u16 sa:1;
85 u16 la:1;
86 u16 ca:1;
[all...]
H A Dcthw20k2.c1 // SPDX-License-Identifier: GPL-2.0-only
76 * Fixed-point value in 8.24 format for parameter channel */
82 u16 ctl:1;
83 u16 ccr:1;
84 u16 sa:1;
85 u16 la:1;
86 u16 ca:1;
87 u16 mpr:1;
88 u16 czbfs:1; /* Clear Z-Buffers */
107 u16 enb0:1;
[all …]
/linux/sound/soc/codecs/
H A Dtfa989x.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
23 #define TFA989X_I2SREG_RCV 2 /* receiver mode */
34 #define TFA989X_SYS_CTRL_I2CR 1 /* I2C reset */
90 SND_SOC_DAPM_SUPPLY("POWER", TFA989X_SYS_CTRL, TFA989X_SYS_CTRL_PWDN, 1, NULL, 0),
95 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
111 gpiod_set_value_cansleep(tfa989x->rcv_gpiod, ucontrol->value.enumerated.item[0]); in tfa989x_put_mode()
116 static const char * const mode_text[] = { "Speaker", "Receiver" };
126 if (tfa989x->rev->rev == TFA9897_REVISION) in tfa989x_probe()
139 .use_pmdown_time = 1,
[all …]
/linux/sound/i2c/
H A Dcs8427.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic
23 MODULE_DESCRIPTION("IEC958 (S/PDIF) receiver & transmitter by Cirrus Logic");
26 #define CS8427_ADDR (0x20>>1) /* fixed address */
38 unsigned char regmap[0x14]; /* map of first 1 + 13 registers */
52 buf[1] = val; in snd_cs8427_reg_write()
55 dev_err(device->bus->card->dev, in snd_cs8427_reg_write()
57 buf[0], buf[1], err); in snd_cs8427_reg_write()
58 return err < 0 ? err : -EIO; in snd_cs8427_reg_write()
70 err = snd_i2c_sendbytes(device, &reg, 1); in snd_cs8427_reg_read()
[all …]
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]

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