Searched +full:i2c +full:- +full:scl +full:- +full:clk +full:- +full:low +full:- +full:timeout +full:- +full:us (Results 1 – 4 of 4) sorted by relevance
1 /*-2 * SPDX-License-Identifier: BSD-2-Clause31 * Driver for the I2C module on the TI SoC.72 * I2C device driver context, a pointer to this is stored in the device101 uint8_t scll; /* Fast/Standard mode SCL low time */102 uint8_t sclh; /* Fast/Standard mode SCL high time */103 uint8_t hsscll; /* High Speed mode SCL low time */104 uint8_t hssclh; /* High Speed mode SCL high time */109 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))123 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)9 #include "stm32mp15-pinctrl.dtsi"10 #include "stm32mp15xxac-pinctrl.dtsi"11 #include <dt-bindings/gpio/gpio.h>12 #include <dt-bindings/mfd/st,stpmic1.h>23 stdout-path = "serial0:115200n8";31 reserved-memory {32 #address-cell[all...]
1 /*-2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk33 * I2C driver for Freescale i.MX hardware.36 * This driver currently implements only master-mode operations.38 * This driver supports multi-master i2c buses, by detecting bus arbitration41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller78 #include <dev/clk/clk.h>81 #define I2C_ADDR_REG 0x00 /* I2C slave address register */82 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */83 #define I2C_CONTROL_REG 0x08 /* I2C control register */[all …]
2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…116 … (0x1<<9) // Fast back-to-back transaction ena…128 … (0x1<<23) // Fast back-to-back capable. Not ap…145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…[all …]