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/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cell
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/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmicrochip-mpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
6 #include "microchip-mpfs-fabric.dtsi"
9 #address-cells = <2>;
10 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
21 i-cache-block-size = <64>;
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H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/freebsd/stand/common/
H A Dbcache.c1 /*-
30 * Simple hashed block cache
56 * bcache per device node. cache is allocated on device first open and freed
57 * on last close, to save memory. The issue there is the size; biosdisk
74 static u_int bcache_units; /* number of devices with cache */
83 #define BHASH(bc, blkno) ((blkno) & ((bc)->bcache_nblks - 1))
85 ((bc)->bcache_ctl[BHASH((bc), (blkno))].bc_blkno != (blkno))
95 * Initialise the cache for (nblks) of (bsize).
106 * add number of devices to bcache. we have to divide cache space
122 u_int i; in bcache_allocate() local
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/freebsd/sys/contrib/device-tree/src/riscv/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/freebsd/sbin/dump/
H A Dcache.c2 * CACHE.C
4 * Block cache for dump
35 typedef struct Block { struct
36 struct Block *b_HNext; /* must be first field */ argument
39 } Block; typedef
45 static Block **BlockHash;
53 int i; in cinit() local
55 Block *base; in cinit()
57 if ((BlockSize = sblock->fs_bsize * BLKFACTOR) > MAXBSIZE) in cinit()
62 msg("Cache %d MB, blocksize = %d\n", in cinit()
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/freebsd/sys/contrib/openzfs/man/man8/
H A Dzdb.81 .\" SPDX-License-Identifier: CDDL-1.0
29 .Op Fl I Ar inflight-I/O-ops
32 .Op Fl U Ar cache
35 .Op Ar poolname Ns Op / Ns Ar dataset Ns | Ns Ar objset-ID
40 .Op Fl U Ar cache
42 .Ar poolname Ns Op Ar / Ns Ar dataset Ns | Ns Ar objset-ID
47 .Op Fl U Ar cache
49 .Ar poolname Ns Ar / Ns Ar objset-ID
50 .Op Ar backup-flags
54 .Op Fl U Ar cache
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DMemoryDependenceAnalysis.cpp1 //===- MemoryDependenceAnalysis.cpp - Mem Deps Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
59 STATISTIC(NumCacheNonLocal, "Number of fully cached non-local responses");
60 STATISTIC(NumCacheDirtyNonLocal, "Number of dirty cached non-local responses");
61 STATISTIC(NumUncacheNonLocal, "Number of uncached non-local responses");
64 "Number of fully cached non-local ptr responses");
66 "Number of cached, but dirty, non-local ptr responses");
67 STATISTIC(NumUncacheNonLocalPtr, "Number of uncached non-local ptr responses");
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/freebsd/sys/contrib/device-tree/src/riscv/kendryte/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/k210-clk.h>
10 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13 #address-cells = <1>;
14 #size-cells = <1>;
23 * Since this is a non-ratified draft specification, the kernel does not
28 #address-cells = <1>;
29 #size-cells = <0>;
30 timebase-frequency = <7800000>;
36 mmu-type = "none";
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/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/freebsd/sys/dev/mlx5/mlx5_core/
H A Dmlx5_cmd.c1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
32 #include <linux/dma-mapping.h>
36 #include <linux/io-mapping.h>
43 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size);
107 return ERR_PTR(-ENOMEM); in alloc_cmd()
109 ent->in = in; in alloc_cmd()
110 ent->uin_size = uin_size; in alloc_cmd()
111 ent->out = out; in alloc_cmd()
112 ent->uout = uout; in alloc_cmd()
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
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H A Dmicrowatt.dts1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
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/freebsd/usr.sbin/ctladm/
H A Dctladm.83 .\" Copyright (c) 2015-2021 Alexander Motin <mav@FreeBSD.org>
36 .\" $Id: //depot/users/kenm/FreeBSD-test2/usr.sbin/ctladm/ctladm.8#3 $
72 .Aq Fl f Ar file|-
82 .Aq Fl f Ar file|-
98 .Op Fl c Ar size
103 .Op Fl i
109 .Op Fl i
118 .Op Fl i
130 .Aq Fl i Ar action
176 .Op Fl i
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/freebsd/sys/contrib/device-tree/src/riscv/allwinner/
H A Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cell
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/freebsd/sys/contrib/device-tree/src/sh/
H A Dj2_mimas_v2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "jcore,j2-soc";
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&aic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-frequency = <50000000>;
22 d-cache-size = <8192>;
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/freebsd/share/doc/papers/sysperf/
H A D4.t54 Where possible, we have allowed the size of caches to be controlled
62 translating path names to inodes\u\s-21\s0\d\**.
64 \** \u\s-21\s0\d Inode is an abbreviation for ``Index node''.
84 Changing directories invalidates the cache, as
95 The cost of the cache is about 20 lines of code
101 cache we ran ``ls \-l''
103 Before the per-process cache this command
105 After adding the cache the program used the same amount
129 Table 9. Call times for \fInamei\fP with per-process cache.
134 was caused by a low cache hit ratio.
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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DJITLink.cpp1 //===------------- JITLink.cpp - Core Run-time JIT linker APIs ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
68 return "Keep-Alive"; in getGenericEdgeKindName()
96 bool isCStringBlock(Block &B) { in isCStringBlock()
97 if (B.getSize() == 0) // Empty blocks are not valid C-strings. in isCStringBlock()
100 // Zero-fill blocks of size one are valid empty strings. in isCStringBlock()
104 for (size_t I = 0; I != B.getSize() - 1; ++I) in isCStringBlock() local
105 if (B.getContent()[I] == '\0') in isCStringBlock()
108 return B.getContent()[B.getSize() - 1] == '\0'; in isCStringBlock()
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/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/
H A DSectionMemoryManager.h1 //===- SectionMemoryManager.h - Memory manager for MCJIT/RtDyld -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the declaration of a section-based memory manager used by
12 //===----------------------------------------------------------------------===//
27 /// the RuntimeDyld class to allocate memory for section-based loading of
30 /// This memory manager allocates all section memory as read-write. The
34 /// Any client using this memory manager MUST ensure that section-specific
55 /// case an attempt is made to allocate more memory near the existing block.
58 /// block of the memory. \p EC [out] returns an object describing any error
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/freebsd/sys/contrib/openzfs/module/zfs/
H A Ddbuf.c1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
65 * Various statistics about the size of the dbuf cache.
71 * Statistics regarding the bounds on the dbuf cache size.
77 * Total number of dbuf cache evictions that have occurred.
81 * The distribution of dbuf levels in the dbuf cache and
82 * the total size of all dbufs at each level.
110 * Statistics about the size of the metadata dbuf cache.
117 * something to the metadata cache because it's full, and instead put
118 * the data in the regular dbuf cache.
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/freebsd/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_dense_alloc.h1 //===-- tsan_dense_alloc.h --------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // A DenseSlabAlloc is a freelist-based allocator of fixed-size objects.
12 // DenseSlabAllocCache is a thread-local cache for DenseSlabAlloc.
17 //===----------------------------------------------------------------------===//
30 IndexT cache[kSize]; variable
38 typedef DenseSlabAllocCache Cache; typedef
39 typedef typename Cache::IndexT IndexT;
41 static_assert((kL1Size & (kL1Size - 1)) == 0,
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/freebsd/share/man/man9/
H A Dbuf.933 .Nd "kernel buffer I/O scheme used in FreeBSD VM system"
35 The kernel implements a KVM abstraction of the buffer cache which allows it
37 (mainly file system) devices and device I/O.
39 block sizes from DEV_BSIZE (usually 512) to upwards of several pages or more.
40 It also supports a relatively primitive byte-granular valid range and dirty
48 cache.
53 *block* aligned.
57 Finally, the VM system's core buffer cache supports
58 valid and dirty bits (m->valid, m->dirt
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