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/linux/drivers/net/ethernet/intel/igb/
H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
10 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
11 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
13 static s32 igb_wait_autoneg(struct e1000_hw *hw);
14 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
31 * igb_check_reset_block - Check if PHY reset is blocked
32 * @hw: pointer to the HW structure
38 s32 igb_check_reset_block(struct e1000_hw *hw) in igb_check_reset_block() argument
48 * igb_get_phy_id - Retrieve the PHY ID and revision
[all …]
H A De1000_mbx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
7 * igb_read_mbx - Reads a message from the mailbox
8 * @hw: pointer to the HW structure
16 s32 igb_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id, in igb_read_mbx() argument
19 struct e1000_mbx_info *mbx = &hw->mbx; in igb_read_mbx()
20 s32 ret_val = -E1000_ERR_MBX; in igb_read_mbx()
23 if (size > mbx->size) in igb_read_mbx()
24 size = mbx->size; in igb_read_mbx()
26 if (mbx->ops.read) in igb_read_mbx()
[all …]
/linux/drivers/clk/meson/
H A Da1-peripherals.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
13 #include "clk-dualdiv.h"
14 #include "clk-regmap.h"
15 #include "meson-clkc-utils.h"
17 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
54 .hw.init = &(struct clk_init_data) {
56 .ops = &clk_regmap_gate_ro_ops,
69 .hw.init = &(struct clk_init_data) {
71 .ops = &clk_regmap_gate_ro_ops,
[all …]
H A Dmeson8b.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
19 #include "clk-regmap.h"
20 #include "meson-clkc-utils.h"
21 #include "clk-pll.h"
22 #include "clk-mpll.h"
24 #include <dt-bindings/clock/meson8b-clkc.h>
25 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
155 .hw.init = &(struct clk_init_data){
[all …]
H A Daxg.c1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
21 #include "meson-clkc-utils.h"
23 #include <dt-bindings/clock/axg-clkc.h>
144 .hw.init = &(struct clk_init_data){
146 .ops = &meson_clk_pll_ro_ops,
[all …]
/linux/sound/pci/ctxfi/
H A Dctsrc.c1 // SPDX-License-Identifier: GPL-2.0-only
36 struct hw *hw; in src_set_state() local
38 hw = src->rsc.hw; in src_set_state()
39 hw->src_set_state(src->rsc.ctrl_blk, state); in src_set_state()
46 struct hw *hw; in src_set_bm() local
48 hw = src->rsc.hw; in src_set_bm()
49 hw->src_set_bm(src->rsc.ctrl_blk, bm); in src_set_bm()
56 struct hw *hw; in src_set_sf() local
58 hw = src->rsc.hw; in src_set_sf()
59 hw->src_set_sf(src->rsc.ctrl_blk, sf); in src_set_sf()
[all …]
/linux/drivers/clk/qcom/
H A Dnsscc-ipq9574.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
10 #include <linux/interconnect-provider.h>
20 #include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
21 #include <dt-bindings/interconnect/qcom,ipq9574.h>
22 #include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
24 #include "clk-alpha-pll.h"
25 #include "clk-branch.h"
26 #include "clk-pll.h"
27 #include "clk-rcg.h"
[all …]
H A Dgcc-msm8996.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
19 #include "clk-regmap.h"
20 #include "clk-alpha-pll.h"
21 #include "clk-rcg.h"
22 #include "clk-branch.h"
38 .hw.init = &(struct clk_init_data){
44 .ops = &clk_fixed_factor_ops,
[all …]
H A Dgcc-sc8280xp.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
18 #include "clk-alpha-pll.h"
19 #include "clk-branch.h"
20 #include "clk-rcg.h"
21 #include "clk-regmap.h"
22 #include "clk-regmap-divider.h"
23 #include "clk-regmap-mux.h"
24 #include "clk-regmap-phy-mux.h"
[all …]
H A Dgcc-sm8250.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
41 .hw.init = &(struct clk_init_data){
47 .ops = &clk_alpha_pll_fixed_lucid_ops,
[all …]
H A Dgcc-sm6375.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap.h"
19 #include "clk-regmap-divider.h"
20 #include "clk-regmap-mux.h"
21 #include "clk-regmap-phy-mux.h"
[all …]
H A Dgcc-sdm660.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
13 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
20 #include "clk-regmap.h"
21 #include "clk-alpha-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
40 .hw.init = &(struct clk_init_data){
[all …]
H A Dgcc-qcs8300.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-pll.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "clk-regmap-mux.h"
[all …]
H A Dgcc-msm8939.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
17 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
20 #include "clk-regmap.h"
21 #include "clk-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
60 .clkr.hw.init = &(struct clk_init_data){
[all …]
H A Dgcc-sm6115.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
15 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
17 #include "clk-alpha-pll.h"
18 #include "clk-branch.h"
19 #include "clk-pll.h"
20 #include "clk-rcg.h"
21 #include "clk-regmap.h"
[all …]
H A Dgcc-sa8775p.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "clk-regmap-mux.h"
[all …]
H A Dgcc-sm6125.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
15 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
17 #include "clk-alpha-pll.h"
18 #include "clk-branch.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
47 .hw.init = &(struct clk_init_data){
53 .ops = &clk_alpha_pll_ops,
[all …]
H A Dgcc-msm8916.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
17 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
20 #include "clk-regmap.h"
21 #include "clk-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
52 .clkr.hw.init = &(struct clk_init_data){
[all …]
H A Dgcc-msm8909.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on gcc-msm8916.c:
7 * adapted with data from clock-gcc-8909.c in Qualcomm's msm-3.18 release:
8 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
12 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/qcom,gcc-msm8909.h>
23 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
25 #include "clk-pll.h"
[all …]
H A Dgcc-sm6350.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
40 .hw.init = &(struct clk_init_data){
[all …]
H A Dgcc-ipq5332.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/interconnect-provider.h>
13 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
14 #include <dt-bindings/interconnect/qcom,ipq5332.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
[all …]
H A Dgcc-msm8998.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
19 #include "clk-regmap.h"
20 #include "clk-alpha-pll.h"
21 #include "clk-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
43 .hw.init = &(struct clk_init_data){
[all …]
H A Dgcc-sc7280.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap-divider.h"
20 #include "clk-regmap-mux.h"
21 #include "clk-regmap-phy-mux.h"
[all …]
H A Dgcc-qcs404.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
12 #include <linux/reset-controller.h>
14 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-pll.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
53 { .index = DT_XO, .name = "xo-board" },
[all …]
/linux/drivers/net/ethernet/intel/igbvf/
H A Dvf.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009 - 2018 Intel Corporation. */
8 static s32 e1000_check_for_link_vf(struct e1000_hw *hw);
9 static s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
11 static s32 e1000_init_hw_vf(struct e1000_hw *hw);
12 static s32 e1000_reset_hw_vf(struct e1000_hw *hw);
14 static void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *,
18 static s32 e1000_set_uc_addr_vf(struct e1000_hw *hw, u32 subcmd, u8 *addr);
22 * e1000_init_mac_params_vf - Inits MAC params
23 * @hw: pointer to the HW structure
[all …]

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