Home
last modified time | relevance | path

Searched full:hsp (Results 1 – 25 of 32) sorted by relevance

12

/linux/drivers/mailbox/
H A Dtegra-hsp.c17 #include <dt-bindings/mailbox/tegra186-hsp.h>
56 struct tegra_hsp *hsp; member
132 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset) in tegra_hsp_readl() argument
134 return readl(hsp->regs + offset); in tegra_hsp_readl()
137 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value, in tegra_hsp_writel() argument
140 writel(value, hsp->regs + offset); in tegra_hsp_writel()
165 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master) in __tegra_hsp_doorbell_get() argument
169 list_for_each_entry(entry, &hsp->doorbells, list) in __tegra_hsp_doorbell_get()
177 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master) in tegra_hsp_doorbell_get() argument
182 spin_lock_irqsave(&hsp->lock, flags); in tegra_hsp_doorbell_get()
[all …]
H A DMakefile58 obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
/linux/Documentation/devicetree/bindings/mailbox/
H A Dnvidia,tegra186-hsp.yaml4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
7 title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
14 The HSP modules are used for the processors to share resources and
21 The features that HSP supported are shared mailboxes, shared
25 contain two cells. The first cell determines the HSP type and the
53 mailboxes may vary by instance of the HSP block and SoC
59 <dt-bindings/mailbox/tegra186-hsp.h>
65 - nvidia,tegra186-hsp
66 - nvidia,tegra194-hsp
67 - nvidia,tegra264-hsp
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Deswin,eic7700-usb.yaml52 eswin,hsp-sp-csr:
54 HSP CSR is to control and get status of different high-speed peripherals
60 - description: phandle to HSP Register Controller hsp_sp_csr node.
73 - eswin,hsp-sp-csr
94 eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x818>;
/linux/Documentation/devicetree/bindings/net/
H A Deswin,eic7700-eth.yaml96 eswin,hsp-sp-csr:
98 HSP CSR is to control and get status of different high-speed peripherals
103 and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
114 - description: Phandle to HSP(High-Speed Peripheral) device
133 - eswin,hsp-sp-csr
150 eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>;
176 eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>;
/linux/drivers/clk/eswin/
H A DKconfig18 tristate "EIC7700 HSP Clock Driver"
26 HSP. The clock controller generates and supplies clocks to high
28 Say yes here to support the clock controller on the EIC7700 HSP.
H A Dclk-eic7700-hsp.c6 * ESWIN EIC7700 HSP Clock Driver
319 adev = devm_auxiliary_device_create(dev, "hsp-reset", NULL); in eic7700_hsp_clk_probe()
322 "register hsp-reset device failed\n"); in eic7700_hsp_clk_probe()
336 .name = "eic7700-hsp-clock",
345 MODULE_DESCRIPTION("ESWIN EIC7700 HSP clock controller driver");
H A DMakefile9 obj-$(CONFIG_COMMON_CLK_EIC7700_HSP) += clk-eic7700-hsp.o
/linux/Documentation/devicetree/bindings/clock/
H A Deswin,eic7700-hspcrg.yaml7 title: ESWIN EIC7700 HSP Clock and Reset Generator
13 Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals).
24 - description: HSP configuration top clock
H A Dimx35-clock.yaml24 hsp 5
H A Dimx31-clock.yaml26 hsp 7
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-eic7700.c267 "eswin,hsp-sp-csr"); in eic7700_dwmac_probe()
271 "Failed to get hsp-sp-csr regmap\n"); in eic7700_dwmac_probe()
274 "eswin,hsp-sp-csr", in eic7700_dwmac_probe()
281 "eswin,hsp-sp-csr", in eic7700_dwmac_probe()
288 "eswin,hsp-sp-csr", in eic7700_dwmac_probe()
295 "eswin,hsp-sp-csr", in eic7700_dwmac_probe()
301 "eswin,hsp-sp-csr", in eic7700_dwmac_probe()
/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml26 - .../mailbox/nvidia,tegra186-hsp.yaml
143 #include <dt-bindings/mailbox/tegra186-hsp.h>
146 hsp_top0: hsp@3c00000 {
147 compatible = "nvidia,tegra186-hsp";
202 #include <dt-bindings/mailbox/tegra186-hsp.h>
/linux/drivers/video/fbdev/kyro/
H A DSTG4000VTG.c159 if ((pTiming->HSP > 0) && (pTiming->VSP < 0)) { /* +hsync -vsync */ in SetupVTG()
161 } else if ((pTiming->HSP < 0) && (pTiming->VSP > 0)) { /* -hsync +vsync */ in SetupVTG()
163 } else if ((pTiming->HSP < 0) && (pTiming->VSP < 0)) { /* -hsync -vsync */ in SetupVTG()
165 } else if ((pTiming->HSP > 0) && (pTiming->VSP > 0)) { /* +hsync -vsync */ in SetupVTG()
/linux/drivers/reset/
H A Dreset-eic7700-hsp.c6 * ESWIN EIC7700 HSP Reset Driver
99 { .name = "clk_eic7700_hsp.hsp-reset", },
113 MODULE_DESCRIPTION("ESWIN EIC7700 HSP Reset Controller Driver");
H A DKconfig87 tristate "EIC7700 HSP Reset controller"
91 This enables the HSP reset controller driver for ESWIN SoCs. This
H A DMakefile18 obj-$(CONFIG_RESET_EIC7700_HSP) += reset-eic7700-hsp.o
/linux/drivers/clk/imx/
H A Dclk-imx35.c64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
125 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); in _mx35_clocks_init()
129 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); in _mx35_clocks_init()
190 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); in _mx35_clocks_init()
/linux/include/dt-bindings/reset/
H A Deswin,eic7700-hspcrg.h6 * Device Tree binding constants for EIC7700 HSP reset controller.
/linux/include/dt-bindings/clock/
H A Deswin,eic7700-hspcrg.h6 * Device Tree binding constants for EIC7700 HSP clock controller.
/linux/include/dt-bindings/mailbox/
H A Dtegra186-hsp.h3 * This header provides constants for binding nvidia,tegra186-hsp.
/linux/drivers/phy/eswin/
H A Dphy-eic7700-sata.c210 * address region of the SATA-PHY falls into the region of the HSP in eic7700_sata_phy_probe()
211 * clock & reset that has already been obtained by the HSP in eic7700_sata_phy_probe()
/linux/Documentation/devicetree/bindings/serial/
H A Dnvidia,tegra194-tcu.yaml54 #include <dt-bindings/mailbox/tegra186-hsp.h>
/linux/include/video/
H A Dkyro.h23 s32 HSP; /* Hor Sync Polarity */ member
/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h133 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */
134 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */

12