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Searched +full:hpd +full:- +full:reliable +full:- +full:delay +full:- +full:ms (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-edp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-edp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without
17 board, either for second-sourcing purposes or to support multiple SKUs
51 :<T1>:<T2>: :<--T10-->:<T11>:<T12>:
52 : +-----------------------+---------+---------+
53 eDP -----------+ Black video | Src vid | Blk vid +
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hpd.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/delay.h>
65 const struct hdmi_platform_config *config = hdmi->config; in enable_hpd_clocks()
66 struct device *dev = &hdmi->pdev->dev; in enable_hpd_clocks()
70 for (i = 0; i < config->hpd_clk_cnt; i++) { in enable_hpd_clocks()
71 if (config->hpd_freq && config->hpd_freq[i]) { in enable_hpd_clocks()
72 ret = clk_set_rate(hdmi->hpd_clks[i], in enable_hpd_clocks()
73 config->hpd_freq[i]); in enable_hpd_clocks()
77 config->hpd_clk_names[i], ret); in enable_hpd_clocks()
80 ret = clk_prepare_enable(hdmi->hpd_clks[i]); in enable_hpd_clocks()
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/linux/drivers/gpu/drm/panel/
H A Dpanel-edp.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 #include <linux/delay.h>
46 * struct panel_delay - Describes delays for a simple panel.
50 * @hpd_reliable: Time for HPD to be reliable
53 * before the HPD signal is reliable. Ideally this is 0 but some panels,
57 * Presumably some old panels simply didn't have HPD hooked up and put
59 * hpd_absent. While that works, it's non-ideal.
64 * @hpd_absent: Time to wait if HPD isn't hooked up.
66 * Add this to the prepare delay if we know Hot Plug Detect isn't used.
68 * This is T3-max on eDP timing diagrams or the delay from power on
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/linux/arch/arm64/boot/dts/qcom/
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
37 /* FIXED REGULATORS - parents above children */
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp.c93 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
122 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
134 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
142 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
146 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
150 * rate -> channel coding.
158 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
172 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); in max_dprx_rate()
174 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in max_dprx_rate()
180 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); in max_dprx_lane_count()
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H A Dintel_ddi.c99 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
101 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
127 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
130 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
136 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
141 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
143 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_hdmi_ddi_buffers()
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H A Dintel_psr.c49 * Since Haswell Display controller supports Panel Self-Refresh on display
63 * The implementation uses the hardware-based PSR support which automatically
64 * enters/exits self-refresh mode. The hardware takes care of sending the
67 * changes to know when to exit self-refresh mode again. Unfortunately that
72 * issues the self-refresh re-enable code is done from a work queue, which
80 * entry/exit allows the HW to enter a low-power state even when page flipping
96 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
160 * In standby mode (as opposed to link-off) this makes no difference
174 * The rest of the bits are more self-explanatory and/or
194 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
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