| /linux/tools/testing/selftests/bpf/benchs/ |
| H A D | bench_count.c | 8 struct counter hits; member
16 atomic_inc(&ctx->hits.value); in count_global_producer()
25 res->hits = atomic_swap(&ctx->hits.value, 0); in count_global_measure()
31 struct counter *hits; member
38 ctx->hits = calloc(env.producer_cnt, sizeof(*ctx->hits)); in count_local_setup()
39 if (!ctx->hits) in count_local_setup()
49 atomic_inc(&ctx->hits[idx].value); in count_local_producer()
60 res->hits += atomic_swap(&ctx->hits[i].value, 0); in count_local_measure()
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| H A D | run_common.sh | 21 function hits() function
23 echo "$*" | sed -E "s/.*hits\s+([0-9]+\.[0-9]+ ± [0-9]+\.[0-9]+M\/s).*/\1/"
46 echo -n "hits throughput: "
47 echo -n "$*" | sed -E "s/.* hits throughput\s+([0-9]+\.[0-9]+ ± [0-9]+\.[0-9]+\sM\sops\/s).*/\1/"
48 echo -n -e ", hits latency: "
49 echo -n "$*" | sed -E "s/.* hits latency\s+([0-9]+\.[0-9]+\sns\/op).*/\1/"
63 printf "%-20s %s (drops %s)\n" "$bench" "$(hits $summary)" "$(drops $summary)"
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| H A D | bench_local_storage_create.c | 142 res->hits = atomic_swap(&skel->bss->create_cnts, 0); in measure()
208 creates_per_sec = res->hits / 1000.0 / (delta_ns / 1000000000.0); in report_progress()
209 kmallocs_per_create = (double)res->drops / res->hits; in report_progress()
225 creates_mean += res[i].hits / 1000.0 / (0.0 + res_cnt); in report_final()
226 total_creates += res[i].hits; in report_final()
232 creates_stddev += (creates_mean - res[i].hits / 1000.0) * in report_final()
233 (creates_mean - res[i].hits / 1000.0) / in report_final()
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| H A D | bench_rename.c | 10 struct counter hits; member
37 atomic_inc(&ctx.hits.value); in producer()
43 res->hits = atomic_swap(&ctx.hits.value, 0); in measure()
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| /linux/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/ |
| H A D | uncore-l3c.json | 19 "BriefDescription": "Total read hits",
20 "PublicDescription": "Total read hits",
26 "BriefDescription": "Total write hits",
27 "PublicDescription": "Total write hits",
54 "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
55 "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",
61 "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",
62 "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",
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| /linux/tools/testing/selftests/bpf/ |
| H A D | bench.c | 41 long total = res->false_hits + res->hits + res->drops; in false_hits_report_progress()
46 printf("%ld false hits of %ld total operations. Percentage = %2.2f %%\n", in false_hits_report_progress()
56 total_hits += res[i].hits; in false_hits_report_final()
62 printf("Summary: %ld false hits of %ld total operations. ", in false_hits_report_final()
73 hits_per_sec = res->hits / 1000000.0 / (delta_ns / 1000000000.0); in hits_drops_report_progress()
80 printf("hits %8.3lfM/s (%7.3lfM/prod), drops %8.3lfM/s, total operations %8.3lfM/s\n", in hits_drops_report_progress()
129 hits_mean += res[i].hits / 1000000.0 / (0.0 + res_cnt); in hits_drops_report_final()
136 hits_stddev += (hits_mean - res[i].hits / 1000000.0) * in hits_drops_report_final()
137 (hits_mean - res[i].hits / 1000000.0) / in hits_drops_report_final()
142 total_ops = res[i].hits + res[i].drops; in hits_drops_report_final()
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/ |
| H A D | cache.json | 105 …"PublicDescription": "This event counts operations where demand access hits an L2 cache refill buf…
108 …"BriefDescription": "This event counts operations where demand access hits an L2 cache refill buff…
111 …"PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 …
114 …"BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 c…
117 …"PublicDescription": "This event counts operations where demand access hits an L2 cache refill buf…
120 …"BriefDescription": "This event counts operations where demand access hits an L2 cache refill buff…
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| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | cache.json | 147 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
151 "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
353 …Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cach…
359 …Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cach…
385 …"BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops r…
391 …"PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops …
460 "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
482 "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
488 "PublicDescription": "Retired load instructions with L2 cache hits as data sources.",
504 "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
[all …]
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| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | metrics.json | 492 …"BriefDescription": "Percentage of L2 load hits per instruction where the L2 experienced a Load-Hi…
504 …"BriefDescription": "Percentage of L2 load hits per instruction where the L2 did not experience a …
510 …"BriefDescription": "Percentage of L2 load hits per instruction where the L2 experienced some conf…
534 …"BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pen…
546 …"BriefDescription": "Percentage of L3 load hits per instruction where the L3 did not experience a …
684 …"BriefDescription": "Percentage of L3 load hits per instruction where the line was brought into th…
1926 …"BriefDescription": "Fraction of hits on any Centaur (local, remote, or distant) on either L4 or D…
1946 … "BriefDescription": "Fraction of hits on a distant chip's Centaur (L4 or DRAM) per L1 load ref",
1971 …"BriefDescription": "Fraction of hits of a line in the M (exclusive) state on the L2 or L3 of a co…
1976 …"BriefDescription": "Fraction of hits of a line in the S state on the L2 or L3 of a core on a dist…
[all …]
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| /linux/tools/perf/pmu-events/arch/test/test_soc/cpu/ |
| H A D | uncore.json | 40 "BriefDescription": "Total read hits",
41 "PublicDescription": "Total read hits",
54 "BriefDescription": "Total cache hits",
55 "PublicDescription": "Total cache hits",
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | tlb.json | 8 …dware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in…
16 …"PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses i…
36 …dware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in…
40 …dware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in…
44 …es caused by memory read operations. This event counts whether the access hits or misses in the TL…
48 …s caused by memory write operations. This event counts whether the access hits or misses in the TL…
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | tlb.json | 8 "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction."
16 "PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in the TLB. This event counts both demand accesses and prefetch or preload generated accesses."
36 "PublicDescription": "Counts level 1 data TLB refills caused by memory read operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an Address Translation (AT) instruction."
40 "PublicDescription": "Counts level 1 data TLB refills caused by data side memory write operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count with an access from an Address Translation (AT) instruction."
44 "PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
48 "PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations."
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | tlb.json | 8 …dware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in…
16 …"PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses i…
36 …dware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in…
40 …dware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in…
44 …es caused by memory read operations. This event counts whether the access hits or misses in the TL…
48 …s caused by memory write operations. This event counts whether the access hits or misses in the TL…
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| /linux/drivers/cpuidle/governors/ |
| H A D | teo.c | 46 * Two metrics called "hits" and "intercepts" are associated with each bin.
50 * The "hits" metric reflects the relative frequency of situations in which the
70 * - The sum of the "hits" metric for all of the idle states shallower than
124 * @hits: The "hits" metric.
128 unsigned int hits; member
135 * @total: Grand total of the "intercepts" and "hits" metrics for all bins.
192 * Decay the "hits" and "intercepts" metrics for all of the bins and in teo_update()
199 bin->hits -= bin->hits >> DECAY_SHIFT; in teo_update()
214 * length, this is a "hit", so update the "hits" metric for that bin. in teo_update()
219 cpu_data->state_bins[idx_timer].hits += PULSE; in teo_update()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | uncore-cache.json | 147 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in so…
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …e snoop initiated by this Cbox due to processor core memory request which hits a modified line in …
174 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line i…
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 …e snoop initiated by this Cbox due to processor core memory request which hits a non-modified line…
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| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | uncore-cache.json | 147 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in so…
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …e snoop initiated by this Cbox due to processor core memory request which hits a modified line in …
174 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line i…
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 …e snoop initiated by this Cbox due to processor core memory request which hits a non-modified line…
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| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | uncore-cache.json | 147 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in so…
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …e snoop initiated by this Cbox due to processor core memory request which hits a modified line in …
174 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line i…
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 …e snoop initiated by this Cbox due to processor core memory request which hits a non-modified line…
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| H A D | virtual-memory.json | 25 "PublicDescription": "Number of cache load STLB hits. No page walk.",
278 "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
287 "BriefDescription": "Number of DTLB page walker hits in the L2",
296 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
306 "BriefDescription": "Number of DTLB page walker hits in Memory",
380 "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
389 "BriefDescription": "Number of ITLB page walker hits in the L2",
398 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
408 "BriefDescription": "Number of ITLB page walker hits in Memory",
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| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | virtual-memory.json | 11 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de…
72 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor…
125 "BriefDescription": "Counts the number of Extended Page Directory Entry hits.",
129 …"PublicDescription": "Counts the number of Extended Page Directory Entry hits. The Extended Page …
143 "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry hits.",
147 …"PublicDescription": "Counts the number Extended Page Directory Pointer Entry hits. The Extended …
161 …e number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.",
165 … of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Ext…
187 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to an i…
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| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | virtual-memory.json | 11 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de…
72 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor…
125 "BriefDescription": "Counts the number of Extended Page Directory Entry hits.",
129 …"PublicDescription": "Counts the number of Extended Page Directory Entry hits. The Extended Page …
143 "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry hits.",
147 …"PublicDescription": "Counts the number Extended Page Directory Pointer Entry hits. The Extended …
161 …e number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.",
165 … of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Ext…
187 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to an i…
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| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | memory.json | 29 "BriefDescription": "Store-to-load-forward (STLF) hits."
40 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
46 …"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 1…
52 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
58 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
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| /linux/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2_debugfs.c | 62 u32 hits = mvpp2_cls_flow_hits(entry->priv, entry->id); in mvpp2_dbgfs_flow_flt_hits_show() local
64 seq_printf(s, "%u\n", hits); in mvpp2_dbgfs_flow_flt_hits_show()
75 u32 hits = mvpp2_cls_lookup_hits(entry->priv, entry->flow); in mvpp2_dbgfs_flow_dec_hits_show() local
77 seq_printf(s, "%u\n", hits); in mvpp2_dbgfs_flow_dec_hits_show()
194 u32 hits; in mvpp2_dbgfs_flow_c2_hits_show() local
196 hits = mvpp2_cls_c2_hit_count(entry->priv, entry->id); in mvpp2_dbgfs_flow_c2_hits_show()
198 seq_printf(s, "%u\n", hits); in mvpp2_dbgfs_flow_c2_hits_show()
558 debugfs_create_file("hits", 0444, prs_entry_dir, entry, in mvpp2_dbgfs_prs_entry_init()
602 debugfs_create_file("hits", 0444, c2_entry_dir, entry, in mvpp2_dbgfs_c2_entry_init()
633 debugfs_create_file("hits", 0444, flow_tbl_entry_dir, entry, in mvpp2_dbgfs_flow_tbl_entry_init()
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| /linux/tools/testing/selftests/bpf/progs/ |
| H A D | strncmp_bench.c | 14 long hits = 0; variable
39 __sync_add_and_fetch(&hits, 1); in strncmp_no_helper()
47 __sync_add_and_fetch(&hits, 1); in strncmp_helper()
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| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | virtual-memory.json | 25 "PublicDescription": "Number of cache load STLB hits. No page walk.",
278 "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
287 "BriefDescription": "Number of DTLB page walker hits in the L2",
296 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
306 "BriefDescription": "Number of DTLB page walker hits in Memory",
380 "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
389 "BriefDescription": "Number of ITLB page walker hits in the L2",
398 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
408 "BriefDescription": "Number of ITLB page walker hits in Memory",
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| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | recommended.json | 65 "BriefDescription": "All L2 Cache Hits",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
84 "BriefDescription": "L2 Cache Hits from L2 HWPF",
|