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/freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl
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/freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/
H A Dhisilicon.txt2 ----------------------------------------------------
5 - compatible = "hisilicon,hi3660";
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
13 - compatible = "hisilicon,hi3670";
17 - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
21 - compatible = "hisilicon,hi3798cv200";
25 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
29 - compatible = "hisilicon,hi3620-hi4511";
31 Hi6220 SoC
33 - compatible = "hisilicon,hi6220";
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dhi6220-clock.txt1 * Hisilicon Hi6220 Clock Controller
3 Clock control registers reside in different Hi6220 system controllers,
11 - compatible: the compatible should be one of the following strings to
14 - "hisilicon,hi6220-acpu-sctrl"
15 - "hisilicon,hi6220-aoctrl"
16 - "hisilicon,hi6220-sysctrl"
17 - "hisilicon,hi6220-mediactrl"
18 - "hisilicon,hi6220-pmctrl"
19 - "hisilicon,hi6220-stub-clk"
21 - reg: physical base address of the controller and length of memory mapped
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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dhisilicon,hi6220-reset.txt7 The reset controller registers are part of the system-ctl block on
8 hi6220 SoC.
11 - compatible: should be one of the following:
12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
14 - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
15 - reg: should be register base and length as documented in the
17 - #reset-cells: 1, see below
21 compatible = "hisilicon,hi6220-sysctrl", "syscon";
23 #clock-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Hisilicon Hi6220 SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-reset
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