Searched +full:hi3798cv200 +full:- +full:usb2 +full:- +full:phy (Results 1 – 4 of 4) sorted by relevance
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | hisilicon,inno-usb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,inno-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon INNO USB2 PHY
10 - Pengcheng Li <lpc.li@hisilicon.com>
13 The INNO USB2 PHY device should be a child node of peripheral controller that
14 contains the PHY configuration register, and each device supports up to 2 PHY
15 ports which are represented as child nodes of INNO USB2 PHY device.
20 - hisilicon,hi3798cv200-usb2-phy
[all …]
|
| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | hisilicon,histb-xhci.txt | 6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
20 - phys: a list of phandle + phy specifier pairs
[all …]
|
| /linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hi3798cv200.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * DTS File for HiSilicon Hi3798cv200 SoC.
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
15 compatible = "hisilicon,hi3798cv200";
16 interrupt-parent = <&gic>;
[all …]
|
| /linux/drivers/phy/hisilicon/ |
| H A D | phy-hisi-inno-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HiSilicon INNO USB2 PHY Driver.
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
13 #include <linux/phy/phy.h>
61 void __iomem *reg = priv->mmio; in hisi_inno_phy_write_reg()
65 if (priv->type == PHY_TYPE_0) in hisi_inno_phy_write_reg()
78 if (priv->type == PHY_TYPE_0) in hisi_inno_phy_write_reg()
89 /* The phy clk is controlled by the port0 register 0x06. */ in hisi_inno_phy_setup()
94 static int hisi_inno_phy_init(struct phy *phy) in hisi_inno_phy_init() argument
96 struct hisi_inno_phy_port *port = phy_get_drvdata(phy); in hisi_inno_phy_init()
[all …]
|