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/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy.c1 // SPDX-License-Identifier: GPL-2.0+
127 static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_set_polarity() argument
132 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in sun8i_hdmi_phy_set_polarity()
135 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in sun8i_hdmi_phy_set_polarity()
138 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_set_polarity()
142 static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, in sun8i_a83t_hdmi_phy_config() argument
146 unsigned int clk_rate = mode->crtc_clock * 1000; in sun8i_a83t_hdmi_phy_config()
147 struct sun8i_hdmi_phy *phy = data; in sun8i_a83t_hdmi_phy_config() local
149 sun8i_hdmi_phy_set_polarity(phy, mode); in sun8i_a83t_hdmi_phy_config()
151 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_a83t_hdmi_phy_config()
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H A Dsun8i_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); in sun8i_dw_hdmi_encoder_mode_set() local
24 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); in sun8i_dw_hdmi_encoder_mode_set()
33 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_a83t() argument
37 if (mode->clock > 297000) in sun8i_dw_hdmi_mode_valid_a83t()
44 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_h6() argument
52 if (mode->clock > 594000) in sun8i_dw_hdmi_mode_valid_h6()
70 remote = of_graph_get_remote_node(node, 0, -1); in sun8i_dw_hdmi_find_possible_crtcs()
104 struct sun8i_dw_hdmi *hdmi; in sun8i_dw_hdmi_bind() local
107 if (!pdev->dev.of_node) in sun8i_dw_hdmi_bind()
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/linux/Documentation/devicetree/bindings/phy/
H A Damlogic,meson8-hdmi-tx-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 The HDMI TX PHY node should be the child of a syscon node with the
16 compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
23 pattern: "^hdmi-phy@[0-9a-f]+$"
27 - items:
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H A Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
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H A Dqcom,hdmi-phy-other.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8660
17 - qcom,hdmi-phy-8960
18 - qcom,hdmi-phy-8974
19 - qcom,hdmi-phy-8084
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H A Dqcom,hdmi-phy-qmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon QMP HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8996
17 - qcom,hdmi-phy-8998
22 reg-names:
24 - const: hdmi_pll
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <linux/hdmi.h>
20 #include "hdmi.xml.h"
33 struct hdmi { struct
58 struct hdmi_phy *phy; member
67 /* the encoder we are hooked to (outside of hdmi block) */ argument
98 struct hdmi *hdmi; member
103 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
105 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) in hdmi_write() argument
107 writel(data, hdmi->mmio + reg); in hdmi_write()
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H A Dhdmi_bridge.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "hdmi.h"
18 struct drm_device *dev = bridge->dev; in msm_hdmi_power_on()
20 struct hdmi *hdmi = hdmi_bridge->hdmi; in msm_hdmi_power_on() local
23 pm_runtime_resume_and_get(&hdmi->pdev->dev); in msm_hdmi_power_on()
25 if (hdmi->extp_clk) { in msm_hdmi_power_on()
26 DBG("pixclock: %lu", hdmi->pixclock); in msm_hdmi_power_on()
27 ret = clk_set_rate(hdmi->extp_clk, hdmi->pixclock); in msm_hdmi_power_on()
29 DRM_DEV_ERROR(dev->dev, "failed to set extp clk rate: %d\n", ret); in msm_hdmi_power_on()
31 ret = clk_prepare_enable(hdmi->extp_clk); in msm_hdmi_power_on()
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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-a83t-hdmi-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t HDMI PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a83t-hdmi-phy
20 - allwinner,sun8i-h3-hdmi-phy
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H A Dallwinner,sun8i-a83t-dw-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11 IP with Allwinner\'s own PHY IP. It supports audio and video outputs
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
19 - Chen-Yu Tsai <wens@csie.org>
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H A Dbrcm,bcm2711-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM2711 HDMI Controller
10 - Eric Anholt <eric@anholt.net>
15 - brcm,bcm2711-hdmi0
16 - brcm,bcm2711-hdmi1
17 - brcm,bcm2712-hdmi0
18 - brcm,bcm2712-hdmi1
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/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC HDMI
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
13 #include <linux/hdmi.h>
21 #include <linux/dma-mapping.h>
24 #include <media/cec-notifier.h>
26 #include <linux/media-bus-format.h>
40 #include "dw-hdmi-audio.h"
41 #include "dw-hdmi-cec.h"
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H A Ddw-hdmi-qp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
6 * Author: Algea Cao <algea.cao@rock-chips.com>
10 #include <linux/hdmi.h>
29 #include <sound/hdmi-codec.h>
31 #include "dw-hdmi-qp.h"
43 * slow so we pre-compute values we expect to see.
46 * the recommended N values specified in the Audio chapter of the HDMI
93 /* For 297 MHz+ HDMI spec have some other rule for setting N */
102 * These are the CTS values as recommended in the Audio chapter of the HDMI
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/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c1 // SPDX-License-Identifier: GPL-2.0
70 * sti_hdmi_tx3g4c28phy_start - Start hdmi phy macro cell tx3g4c28
72 * @hdmi: pointer on the hdmi internal structure
76 static bool sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi) in sti_hdmi_tx3g4c28phy_start() argument
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
114 * Configure and power up the PHY PLL in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
118 hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG); in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HDMI driver for OMAP5
14 #define DSS_SUBSYS_NAME "HDMI"
32 #include <sound/omap-hdmi-audio.h>
38 static struct omap_hdmi hdmi; variable
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
60 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
76 * time, turn off the PHY, clear interrupts, and restart, which in hdmi_irq_handler()
85 * setting the PHY to LDOON. To ignore those, we force the RXDET in hdmi_irq_handler()
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H A Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * HDMI driver definition for TI OMAP4 Processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
14 #include <linux/hdmi.h>
16 #include <sound/omap-hdmi-audio.h>
20 /* HDMI Wrapper */
41 /* HDMI WP IRQ flags */
56 /* HDMI PLL */
68 /* HDMI PHY */
276 /* HDMI wrapper funcs */
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <markyao0591@gmail.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
14 with a companion PHY IP.
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
18 - $ref: /schemas/sound/dai-common.yaml#
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define DRIVER_NAME "meson-dw-hdmi"
33 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
36 * DOC: HDMI Output
38 * HDMI Output is composed of :
40 * - A Synopsys DesignWare HDMI Controller IP
41 * - A TOP control block controlling the Clocks and PHY
42 * - A custom HDMI PHY in order convert video to TMDS signal
47 * | HDMI TOP |<= HPD
50 * | Synopsys HDMI | HDMI PHY |=> TMDS
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/linux/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
38 Enable this to support the Rockchip Innosilicon HDMI PHY.
49 Support for Rockchip USB2.0 PHY with Innosilicon IP block.
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/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8mp-hdmi-tx.c1 // SPDX-License-Identifier: GPL-2.0+
25 struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data; in imx8mp_hdmi_mode_valid() local
28 if (mode->clock < 13500) in imx8mp_hdmi_mode_valid()
31 if (mode->clock > 297000) in imx8mp_hdmi_mode_valid()
34 round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000); in imx8mp_hdmi_mode_valid()
35 /* imx8mp's pixel clock generator (fsl-samsung-hdmi) cannot generate in imx8mp_hdmi_mode_valid()
39 * 0.5% = 5/1000 tolerance (mode->clock is 1/1000) in imx8mp_hdmi_mode_valid()
41 if (abs(round_rate - mode->clock * 1000) > mode->clock * 5) in imx8mp_hdmi_mode_valid()
44 /* We don't support double-clocked and Interlaced modes */ in imx8mp_hdmi_mode_valid()
45 if ((mode->flags & DRM_MODE_FLAG_DBLCLK) || in imx8mp_hdmi_mode_valid()
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * HDMI driver definition for TI OMAP4 Processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
14 #include <linux/hdmi.h>
15 #include <sound/omap-hdmi-audio.h>
24 /* HDMI Wrapper */
45 /* HDMI WP IRQ flags */
60 /* HDMI PLL */
72 /* HDMI PHY */
295 /* HDMI wrapper funcs */
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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI Encoder
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
20 - mediatek,mt2701-hdmi
21 - mediatek,mt7623-hdmi
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/arm-smccc.h>
10 #include <linux/hdmi.h>
20 #include <linux/phy/phy.h>
24 #include <sound/hdmi-codec.h>
159 struct phy *phy; member
183 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) in mtk_hdmi_hw_vid_black() argument
185 regmap_update_bits(hdmi->regs, VIDEO_CFG_4, in mtk_hdmi_hw_vid_black()
189 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_hw_make_reg_writable() argument
194 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI in mtk_hdmi_hw_make_reg_writable()
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